topic Re: S32K348 ECC set in S32K

topic Re: S32K348 ECC set in S32K https://community.nxp.com/t5/S32K/S32K348-ECC-set/m-p/2256892#M55208 <P>Hello,</P> <P>ECC tests are part of the eMCEM driver of SAF / SPD package.</P> <P>You will find there examples with sophisticated checks for verification.</P> <P><A href="https://www.nxp.com/design/design-center/software/functional-safety-software/s32-safety-software-framework-saf-and-safety-peripheral-drivers-spd:SAF" target="_blank">https://www.nxp.com/design/design-center/software/functional-safety-software/s32-safety-software-framework-saf-and-safety-peripheral-drivers-spd:SAF</A></P> <P>If you prefer your own code / hard coded tests, then refer to the reference manual:</P> <DIV> <UL> <LI> <DIV style="font-family: 'Segoe UI'; font-size: 14px; font-style: normal; font-weight: 400; line-height: 20px;"> <P>Pre‑reqs:</P> <UL> <LI>RTD clock init configured so ME enables clock to EIM and ERM. If EIM regs don’t respond, it’s almost always a clock gating issue—enable the partition/COFB clock first.</LI> <LI>Startup code initializes ECC for SRAM (write‑through once) before reads, otherwise first read can trigger multi‑bit errors. (Zephyr & SEGGER notes highlight this as a common pitfall.)</LI> <LI>Identify an ERM channel that corresponds to the memory master/region you’ll access (e.g., CM7_0 reading SRAM). Channel mapping is in RM; public tutorials summarize the concept.</LI> </UL> <P>High‑level flow:</P> <OL> <LI>Enable clocks for EIM & ERM</LI> <LI>Configure ERM: enable “single‑bit corrected” interrupt + “multi‑bit error” interrupt for the relevant channel</LI> <LI>Set up EIM: choose the SRAM channel, set one data/check bit for injection (single‑bit)</LI> <LI>Perform a read of any address in that memory region → ERM should report a correctable error</LI> <LI>Clear, then set two bits in EIM (double‑bit)</LI> <LI>Read again → expect non‑correctable → your handler should capture/contain the fault</LI> </OL> <OL> <LI>Optionally, scrub (rewrite) the affected location to clear corrected syndromes</LI> </OL> </DIV> </LI> </UL> <P>Best regards,</P> <P>Peter</P> </DIV> Mon, 08 Dec 2025 07:54:22 GMT petervlna 2025-12-08T07:54:22Z S32K348 ECC set https://community.nxp.com/t5/S32K/S32K348-ECC-set/m-p/2256591#M55198 <P>hello, </P><P>I have three questions that need help to answer, thank you！</P><P>1. can you provide a ecc  sample </P><P>2.  how  can  i  verify the function ?</P> Mon, 08 Dec 2025 02:53:45 GMT https://community.nxp.com/t5/S32K/S32K348-ECC-set/m-p/2256591#M55198 youngkin 2025-12-08T02:53:45Z Re: S32K348 ECC set https://community.nxp.com/t5/S32K/S32K348-ECC-set/m-p/2256892#M55208 <P>Hello,</P> <P>ECC tests are part of the eMCEM driver of SAF / SPD package.</P> <P>You will find there examples with sophisticated checks for verification.</P> <P><A href="https://www.nxp.com/design/design-center/software/functional-safety-software/s32-safety-software-framework-saf-and-safety-peripheral-drivers-spd:SAF" target="_blank">https://www.nxp.com/design/design-center/software/functional-safety-software/s32-safety-software-framework-saf-and-safety-peripheral-drivers-spd:SAF</A></P> <P>If you prefer your own code / hard coded tests, then refer to the reference manual:</P> <DIV> <UL> <LI> <DIV style="font-family: 'Segoe UI'; font-size: 14px; font-style: normal; font-weight: 400; line-height: 20px;"> <P>Pre‑reqs:</P> <UL> <LI>RTD clock init configured so ME enables clock to EIM and ERM. If EIM regs don’t respond, it’s almost always a clock gating issue—enable the partition/COFB clock first.</LI> <LI>Startup code initializes ECC for SRAM (write‑through once) before reads, otherwise first read can trigger multi‑bit errors. (Zephyr & SEGGER notes highlight this as a common pitfall.)</LI> <LI>Identify an ERM channel that corresponds to the memory master/region you’ll access (e.g., CM7_0 reading SRAM). Channel mapping is in RM; public tutorials summarize the concept.</LI> </UL> <P>High‑level flow:</P> <OL> <LI>Enable clocks for EIM & ERM</LI> <LI>Configure ERM: enable “single‑bit corrected” interrupt + “multi‑bit error” interrupt for the relevant channel</LI> <LI>Set up EIM: choose the SRAM channel, set one data/check bit for injection (single‑bit)</LI> <LI>Perform a read of any address in that memory region → ERM should report a correctable error</LI> <LI>Clear, then set two bits in EIM (double‑bit)</LI> <LI>Read again → expect non‑correctable → your handler should capture/contain the fault</LI> </OL> <OL> <LI>Optionally, scrub (rewrite) the affected location to clear corrected syndromes</LI> </OL> </DIV> </LI> </UL> <P>Best regards,</P> <P>Peter</P> </DIV> Mon, 08 Dec 2025 07:54:22 GMT https://community.nxp.com/t5/S32K/S32K348-ECC-set/m-p/2256892#M55208 petervlna 2025-12-08T07:54:22Z