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    <title>topic Re: S32K348 set lockcore in S32K</title>
    <link>https://community.nxp.com/t5/S32K/S32K348-set-lockcore/m-p/2256874#M55205</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;BLOCKQUOTE&gt;1. can you provide a lockcore sample?&lt;/BLOCKQUOTE&gt;
&lt;P&gt;Do you mean lock step programming example?&lt;/P&gt;
&lt;DIV&gt;The S32K348 has dual Arm Cortex-M7 cores, but they are not automatically configured in lockstep. By default, they run in asymmetric or symmetric multiprocessing mode.&lt;/DIV&gt;
&lt;DIV&gt;To switch it to the lockstep, you will program the DCF record -&amp;nbsp;UTEST_MISC[LOCKSTEP_EN].&lt;/DIV&gt;
&lt;DIV&gt;See the DCF clients file attached to reference manual document for more information.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;For programming you can use this example in the thread:&amp;nbsp;&lt;SPAN class="lia-link-navigation lia-attachment-link-disabled lia-link-disabled" aria-disabled="true"&gt;C40_Ip_Example_S32K344.zip&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;A href="https://community.nxp.com/t5/S32K/S32K344-Lock-step-kernel/m-p/1934901" target="_blank"&gt;https://community.nxp.com/t5/S32K/S32K344-Lock-step-kernel/m-p/1934901&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;BLOCKQUOTE&gt;
&lt;P&gt;2. how can i verify the function ?&lt;/P&gt;
&lt;/BLOCKQUOTE&gt;
&lt;P&gt;You can check in the&amp;nbsp;Read-Only GPR On Functional Reset 19 (DCMROF19) register.&lt;/P&gt;
&lt;P&gt;DCM_GPR base address: 402A_C000h&lt;/P&gt;
&lt;P&gt;DCMROF19-offset 348h&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="petervlna_0-1765179477346.png" style="width: 632px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/368906i1B1F979F60AD4F27/image-dimensions/632x121?v=v2" width="632" height="121" role="button" title="petervlna_0-1765179477346.png" alt="petervlna_0-1765179477346.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Peter&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Mon, 08 Dec 2025 07:44:01 GMT</pubDate>
    <dc:creator>petervlna</dc:creator>
    <dc:date>2025-12-08T07:44:01Z</dc:date>
    <item>
      <title>S32K348 set lockcore</title>
      <link>https://community.nxp.com/t5/S32K/S32K348-set-lockcore/m-p/2256552#M55196</link>
      <description>&lt;P&gt;hello,&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have three questions that need help to answer, thank you！&lt;/P&gt;&lt;P&gt;1. can you provide a lockcore&amp;nbsp; sample&amp;nbsp;&lt;/P&gt;&lt;P&gt;2.&amp;nbsp;&amp;nbsp;how&amp;nbsp; can&amp;nbsp; i&amp;nbsp; verify the function ?&lt;/P&gt;</description>
      <pubDate>Mon, 08 Dec 2025 01:57:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K348-set-lockcore/m-p/2256552#M55196</guid>
      <dc:creator>youngkin</dc:creator>
      <dc:date>2025-12-08T01:57:42Z</dc:date>
    </item>
    <item>
      <title>Re: S32K348 set lockcore</title>
      <link>https://community.nxp.com/t5/S32K/S32K348-set-lockcore/m-p/2256874#M55205</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;BLOCKQUOTE&gt;1. can you provide a lockcore sample?&lt;/BLOCKQUOTE&gt;
&lt;P&gt;Do you mean lock step programming example?&lt;/P&gt;
&lt;DIV&gt;The S32K348 has dual Arm Cortex-M7 cores, but they are not automatically configured in lockstep. By default, they run in asymmetric or symmetric multiprocessing mode.&lt;/DIV&gt;
&lt;DIV&gt;To switch it to the lockstep, you will program the DCF record -&amp;nbsp;UTEST_MISC[LOCKSTEP_EN].&lt;/DIV&gt;
&lt;DIV&gt;See the DCF clients file attached to reference manual document for more information.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;For programming you can use this example in the thread:&amp;nbsp;&lt;SPAN class="lia-link-navigation lia-attachment-link-disabled lia-link-disabled" aria-disabled="true"&gt;C40_Ip_Example_S32K344.zip&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;A href="https://community.nxp.com/t5/S32K/S32K344-Lock-step-kernel/m-p/1934901" target="_blank"&gt;https://community.nxp.com/t5/S32K/S32K344-Lock-step-kernel/m-p/1934901&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;BLOCKQUOTE&gt;
&lt;P&gt;2. how can i verify the function ?&lt;/P&gt;
&lt;/BLOCKQUOTE&gt;
&lt;P&gt;You can check in the&amp;nbsp;Read-Only GPR On Functional Reset 19 (DCMROF19) register.&lt;/P&gt;
&lt;P&gt;DCM_GPR base address: 402A_C000h&lt;/P&gt;
&lt;P&gt;DCMROF19-offset 348h&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="petervlna_0-1765179477346.png" style="width: 632px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/368906i1B1F979F60AD4F27/image-dimensions/632x121?v=v2" width="632" height="121" role="button" title="petervlna_0-1765179477346.png" alt="petervlna_0-1765179477346.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Peter&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 08 Dec 2025 07:44:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K348-set-lockcore/m-p/2256874#M55205</guid>
      <dc:creator>petervlna</dc:creator>
      <dc:date>2025-12-08T07:44:01Z</dc:date>
    </item>
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