<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: S32K388 Permanent Lock step(CM7_2) in S32K</title>
    <link>https://community.nxp.com/t5/S32K/S32K388-Permanent-Lock-step-CM7-2/m-p/2239129#M54724</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/257089"&gt;@KiranGowda&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Yes, that is correct. When CM7_0 and CM7_1 are configured in lockstep mode, both cores execute the same instructions simultaneously, and any discrepancy between them will trigger a fault report. Similarly, CM7_2 operates in permanent lockstep with its paired core, meaning it continuously mirrors the same instruction stream and reports any detected fault or error.&lt;/P&gt;</description>
    <pubDate>Fri, 21 Nov 2025 20:11:02 GMT</pubDate>
    <dc:creator>VaneB</dc:creator>
    <dc:date>2025-11-21T20:11:02Z</dc:date>
    <item>
      <title>S32K388 Permanent Lock step(CM7_2)</title>
      <link>https://community.nxp.com/t5/S32K/S32K388-Permanent-Lock-step-CM7-2/m-p/2210067#M54636</link>
      <description>&lt;P&gt;Hi,&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The S32K388 core consists of two types:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;1x LS Cortex-M7 + 3xCortex-M7 @ 320MHz or&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;2x LS Cortex-M7 + 1xCortex-M7 @ 320MHz&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;As per the above configuration, CM7_&lt;STRONG&gt;0&lt;/STRONG&gt; and CM7_&lt;STRONG&gt;1&lt;/STRONG&gt; can be decoupled to work them as two separate cores. However, CM7_2 is in&amp;nbsp;Permanent Lock step core.&lt;/P&gt;&lt;P&gt;Lockstep core means "&lt;SPAN&gt;&amp;nbsp;two processors operate in parallel, executing the same set of instructions simultaneously. The key feature of lockstep is that both cores execute the same instructions and compare their results at every step to ensure they match. If a discrepancy is detected, it indicates a potential error or fault in one of the cores, triggering a fault-handling mechanism."&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I want to know which another core is executing the same set of&amp;nbsp;instructions simultaneously along with CM7_2&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="KiranGowda_0-1763558453914.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/366320iE9F64029EE1D8DB4/image-size/medium?v=v2&amp;amp;px=400" role="button" title="KiranGowda_0-1763558453914.png" alt="KiranGowda_0-1763558453914.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Thanks in advance&lt;/P&gt;</description>
      <pubDate>Wed, 19 Nov 2025 13:21:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K388-Permanent-Lock-step-CM7-2/m-p/2210067#M54636</guid>
      <dc:creator>KiranGowda</dc:creator>
      <dc:date>2025-11-19T13:21:41Z</dc:date>
    </item>
    <item>
      <title>Re: S32K388 Permanent Lock step(CM7_2)</title>
      <link>https://community.nxp.com/t5/S32K/S32K388-Permanent-Lock-step-CM7-2/m-p/2216771#M54650</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/257089"&gt;@KiranGowda&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Since CM7_2 operates in permanent lockstep mode, it is treated as a single entity and cannot be decoupled. This is why the other core is not explicitly named; it is considered part of the same unit.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR, VaneB&lt;/P&gt;</description>
      <pubDate>Wed, 19 Nov 2025 22:14:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K388-Permanent-Lock-step-CM7-2/m-p/2216771#M54650</guid>
      <dc:creator>VaneB</dc:creator>
      <dc:date>2025-11-19T22:14:58Z</dc:date>
    </item>
    <item>
      <title>Re: S32K388 Permanent Lock step(CM7_2)</title>
      <link>https://community.nxp.com/t5/S32K/S32K388-Permanent-Lock-step-CM7-2/m-p/2235251#M54722</link>
      <description>&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/201913"&gt;@VaneB&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;If CM7_0 and CM7_1 are in lockstep core both are executing the same instructions and if any discrepancy it will report . In the similar context CM7_2 is permanent lockstep which another core is executing the same instructions and report if any fault or error.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you&lt;/P&gt;</description>
      <pubDate>Fri, 21 Nov 2025 14:55:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K388-Permanent-Lock-step-CM7-2/m-p/2235251#M54722</guid>
      <dc:creator>KiranGowda</dc:creator>
      <dc:date>2025-11-21T14:55:36Z</dc:date>
    </item>
    <item>
      <title>Re: S32K388 Permanent Lock step(CM7_2)</title>
      <link>https://community.nxp.com/t5/S32K/S32K388-Permanent-Lock-step-CM7-2/m-p/2239129#M54724</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/257089"&gt;@KiranGowda&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Yes, that is correct. When CM7_0 and CM7_1 are configured in lockstep mode, both cores execute the same instructions simultaneously, and any discrepancy between them will trigger a fault report. Similarly, CM7_2 operates in permanent lockstep with its paired core, meaning it continuously mirrors the same instruction stream and reports any detected fault or error.&lt;/P&gt;</description>
      <pubDate>Fri, 21 Nov 2025 20:11:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K388-Permanent-Lock-step-CM7-2/m-p/2239129#M54724</guid>
      <dc:creator>VaneB</dc:creator>
      <dc:date>2025-11-21T20:11:02Z</dc:date>
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  </channel>
</rss>

