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    <title>S32KのトピックRe: ADC Code output Test on real time?</title>
    <link>https://community.nxp.com/t5/S32K/ADC-Code-output-Test-on-real-time/m-p/2229272#M54700</link>
    <description>&lt;P&gt;Thank you for your interest in our products and for contributing to our community.&lt;/P&gt;
&lt;P&gt;Please refer to the following knowledge base post:&lt;/P&gt;
&lt;P&gt;&lt;EM&gt;S32M24x/S32K1 – FTM/TRGMUX/PDB/ADC – [RTD300] -&amp;gt;&lt;/EM&gt; &lt;A href="https://community.nxp.com/t5/S32M-Knowledge-Base/S32M24x-S32K1-FTM-TRGMUX-PDB-ADC-RTD300/ta-p/2229035" target="_blank" rel="noopener"&gt;https://community.nxp.com/t5/S32M-Knowledge-Base/S32M24x-S32K1-FTM-TRGMUX-PDB-ADC-RTD300/ta-p/2229035&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;We hope this resolves your issue.&lt;/P&gt;</description>
    <pubDate>Fri, 21 Nov 2025 05:19:17 GMT</pubDate>
    <dc:creator>_Leo_</dc:creator>
    <dc:date>2025-11-21T05:19:17Z</dc:date>
    <item>
      <title>ADC Code output Test on real time?</title>
      <link>https://community.nxp.com/t5/S32K/ADC-Code-output-Test-on-real-time/m-p/2205050#M54480</link>
      <description>&lt;P&gt;I am running example s32k148 on my s32 ide for arm. Please tell me how to check its output in real time expression and where to configure pins. I am new here in coding and on board.&amp;nbsp; Please guide me by mentioning steps.&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;ADC.c&lt;/STRONG&gt;&lt;/P&gt;&lt;DIV&gt;/*&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* Copyright (c) 2014 - 2016, Freescale Semiconductor, Inc.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* Copyright (c) 2016 - 2018, NXP.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* All rights reserved.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* Redistribution and use in source and binary forms, with or without&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* modification, are permitted provided that the following conditions are met:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* 1. Redistributions of source code must retain the above copyright notice,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*&amp;nbsp; &amp;nbsp; this list of conditions and the following disclaimer.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* 2. Redistributions in binary form must reproduce the above copyright notice,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*&amp;nbsp; &amp;nbsp; this list of conditions and the following disclaimer in the documentation&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*&amp;nbsp; &amp;nbsp; and/or other materials provided with the distribution.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* 3. Neither the name of the copyright holder nor the names of its contributors&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*&amp;nbsp; &amp;nbsp; may be used to endorse or promote products derived from this software&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*&amp;nbsp; &amp;nbsp; without specific prior written permission.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* THE POSSIBILITY OF SUCH DAMAGE.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*/&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;#include "ADC.h"&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;void ADC_init(void)&lt;/DIV&gt;&lt;DIV&gt;{&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;/*!&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;* ADC0 Clocking:&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;* ===================================================&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;*/&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; PCC-&amp;gt;PCCn[PCC_ADC0_INDEX] &amp;amp;=~ PCC_PCCn_CGC_MASK;&amp;nbsp; /* Disable clock to change PCS */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; PCC-&amp;gt;PCCn[PCC_ADC0_INDEX] |= PCC_PCCn_PCS(1);&amp;nbsp; &amp;nbsp; &amp;nbsp;/* PCS=1: Select SOSCDIV2 */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; PCC-&amp;gt;PCCn[PCC_ADC0_INDEX] |= PCC_PCCn_CGC_MASK;&amp;nbsp; &amp;nbsp;/* Enable bus clock in ADC */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;/*!&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;* ADC0 Initialization:&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;* ===================================================&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;*/&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ADC0-&amp;gt;SC1[0] |= ADC_SC1_ADCH_MASK; /* ADCH=1F: Module is disabled for conversions */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* AIEN=0: Interrupts are disabled */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ADC0-&amp;gt;CFG1 |= ADC_CFG1_ADIV_MASK&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;|ADC_CFG1_MODE(1); /* ADICLK=0: Input clk=ALTCLK1=SOSCDIV2 */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* ADIV=0: Prescaler=1 */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* MODE=1: 12-bit conversion */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ADC0-&amp;gt;CFG2 = ADC_CFG2_SMPLTS(12); /* SMPLTS=12(default): sample time is 13 ADC clks */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ADC0-&amp;gt;SC2 = 0x00000000;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* ADTRG=0: SW trigger */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* ACFE,ACFGT,ACREN=0: Compare func disabled */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* DMAEN=0: DMA disabled */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* REFSEL=0: Voltage reference pins= VREFH, VREEFL */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ADC0-&amp;gt;SC3 = 0x00000000;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* CAL=0: Do not start calibration sequence */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* ADCO=0: One conversion performed */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* AVGE,AVGS=0: HW average function disabled */&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;DIV&gt;void ADC_init_HWTrigger(char Channel)&amp;nbsp; {&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; PCC-&amp;gt;PCCn[PCC_ADC0_INDEX] &amp;amp;=~ PCC_PCCn_CGC_MASK;&amp;nbsp; /* Disable clock to change PCS */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; PCC-&amp;gt;PCCn[PCC_ADC0_INDEX] |= PCC_PCCn_PCS(1);&amp;nbsp; &amp;nbsp; &amp;nbsp;/* PCS=1: Select SOSCDIV2 */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; PCC-&amp;gt;PCCn[PCC_ADC0_INDEX] |= PCC_PCCn_CGC_MASK;&amp;nbsp; &amp;nbsp;/* Enable bus clock in ADC */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ADC0-&amp;gt;SC1[0] |= ADC_SC1_ADCH_MASK&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; |ADC_SC1_AIEN_MASK;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/* ADCH=1F: Module is disabled for conversions*/&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* AIEN=0: Interrupts are disabled */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ADC0-&amp;gt;CFG1 |= ADC_CFG1_ADIV_MASK&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; |ADC_CFG1_MODE(1);/* ADICLK=0: Input clk=ALTCLK1=SOSCDIV2 */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* ADIV=0: Prescaler=1 */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* MODE=1: 12-bit conversion */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ADC0-&amp;gt;CFG2 = 0x00000000C;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/* SMPLTS=12(default): sample time is 13 ADC clks */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ADC0-&amp;gt;SC2 = ADC_SC2_ADTRG_MASK;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/* ADTRG=1: HW trigger */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* ACFE,ACFGT,ACREN=0: Compare func disabled */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* DMAEN=0: DMA disabled */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* REFSEL=0: Voltage reference pins= VREFH, VREEFL */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ADC0-&amp;gt;SC1[0] = ADC_SC1_ADCH(Channel)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; |ADC_SC1_AIEN_MASK;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/* ADCH=1F: Module is disabled for conversions*/&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* AIEN=0: Interrupts are disabled */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ADC0-&amp;gt;SC3 = 0x00000000;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/* CAL=0: Do not start calibration sequence */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* ADCO=0: One conversion performed */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* AVGE,AVGS=0: HW average function disabled */&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;void convertAdcChan(uint16_t adcChan)&lt;/DIV&gt;&lt;DIV&gt;{&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;/*!&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;* For SW trigger mode, SC1[0] is used&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;* ===================================================&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;*/&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ADC0-&amp;gt;SC1[0]&amp;amp;=~ADC_SC1_ADCH_MASK; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* Clear prior ADCH bits */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; ADC0-&amp;gt;SC1[0] = ADC_SC1_ADCH(adcChan);&amp;nbsp; &amp;nbsp;/* Initiate Conversion */&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;uint8_t adc_complete(void)&lt;/DIV&gt;&lt;DIV&gt;{&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; return ((ADC0-&amp;gt;SC1[0] &amp;amp; ADC_SC1_COCO_MASK)&amp;gt;&amp;gt;ADC_SC1_COCO_SHIFT); /* Wait for completion */&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;uint32_t read_adc_chx(void)&lt;/DIV&gt;&lt;DIV&gt;{&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; uint16_t adc_result=0;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; adc_result=ADC0-&amp;gt;R[0];&amp;nbsp; &amp;nbsp; &amp;nbsp; /* For SW trigger mode, R[0] is used */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; return&amp;nbsp; (uint32_t) ((5000*adc_result)/0xFFF); /* Convert result to mv for 0-5V range */&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;ADC.h&lt;/STRONG&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;P&gt;#ifndef ADC_H_&lt;BR /&gt;#define ADC_H_&lt;BR /&gt;#include "device_registers.h" /* include peripheral declarations S32K144 */&lt;/P&gt;&lt;P&gt;void convertAdcChan(uint16_t);&lt;BR /&gt;void ADC_init(void);&lt;BR /&gt;void ADC_init_HWTrigger(char Channel);&lt;BR /&gt;uint8_t adc_complete(void);&lt;BR /&gt;uint32_t read_adc_chx(void);&lt;/P&gt;&lt;P&gt;#endif /* ADC_H_ */&lt;/P&gt;&lt;/DIV&gt;</description>
      <pubDate>Fri, 14 Nov 2025 08:55:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/ADC-Code-output-Test-on-real-time/m-p/2205050#M54480</guid>
      <dc:creator>Turtledove</dc:creator>
      <dc:date>2025-11-14T08:55:15Z</dc:date>
    </item>
    <item>
      <title>Re: ADC Code output Test on real time?</title>
      <link>https://community.nxp.com/t5/S32K/ADC-Code-output-Test-on-real-time/m-p/2229272#M54700</link>
      <description>&lt;P&gt;Thank you for your interest in our products and for contributing to our community.&lt;/P&gt;
&lt;P&gt;Please refer to the following knowledge base post:&lt;/P&gt;
&lt;P&gt;&lt;EM&gt;S32M24x/S32K1 – FTM/TRGMUX/PDB/ADC – [RTD300] -&amp;gt;&lt;/EM&gt; &lt;A href="https://community.nxp.com/t5/S32M-Knowledge-Base/S32M24x-S32K1-FTM-TRGMUX-PDB-ADC-RTD300/ta-p/2229035" target="_blank" rel="noopener"&gt;https://community.nxp.com/t5/S32M-Knowledge-Base/S32M24x-S32K1-FTM-TRGMUX-PDB-ADC-RTD300/ta-p/2229035&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;We hope this resolves your issue.&lt;/P&gt;</description>
      <pubDate>Fri, 21 Nov 2025 05:19:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/ADC-Code-output-Test-on-real-time/m-p/2229272#M54700</guid>
      <dc:creator>_Leo_</dc:creator>
      <dc:date>2025-11-21T05:19:17Z</dc:date>
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