<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>S32KのトピックS32K116 ADC - Maximum possible sampling time</title>
    <link>https://community.nxp.com/t5/S32K/S32K116-ADC-Maximum-possible-sampling-time/m-p/965438#M5441</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;in order to reduce my BOM count in a current project, I would like to maximize the sampling time of the ADC. Thereby, I try to achieve that the output impedance of my temperature sensor is sufficient to drive the ADC sampling capacitor incl. analog bus capacitance.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What I already did:&lt;/P&gt;&lt;P&gt;1) Set ADC clock to SIRCDIV2_CLK (8 MHz)&lt;/P&gt;&lt;P&gt;2) Set ADC clock prescaler to 8&lt;/P&gt;&lt;P&gt;3) Set sample ticks to 255&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This should result in a sample time of 256us.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is there a way to further increase the sample time? E.g. using pretrigger and trigger?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Markus&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 24 Oct 2019 12:52:02 GMT</pubDate>
    <dc:creator>markus1</dc:creator>
    <dc:date>2019-10-24T12:52:02Z</dc:date>
    <item>
      <title>S32K116 ADC - Maximum possible sampling time</title>
      <link>https://community.nxp.com/t5/S32K/S32K116-ADC-Maximum-possible-sampling-time/m-p/965438#M5441</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;in order to reduce my BOM count in a current project, I would like to maximize the sampling time of the ADC. Thereby, I try to achieve that the output impedance of my temperature sensor is sufficient to drive the ADC sampling capacitor incl. analog bus capacitance.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What I already did:&lt;/P&gt;&lt;P&gt;1) Set ADC clock to SIRCDIV2_CLK (8 MHz)&lt;/P&gt;&lt;P&gt;2) Set ADC clock prescaler to 8&lt;/P&gt;&lt;P&gt;3) Set sample ticks to 255&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This should result in a sample time of 256us.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is there a way to further increase the sample time? E.g. using pretrigger and trigger?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Markus&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 24 Oct 2019 12:52:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K116-ADC-Maximum-possible-sampling-time/m-p/965438#M5441</guid>
      <dc:creator>markus1</dc:creator>
      <dc:date>2019-10-24T12:52:02Z</dc:date>
    </item>
    <item>
      <title>Re: S32K116 ADC - Maximum possible sampling time</title>
      <link>https://community.nxp.com/t5/S32K/S32K116-ADC-Maximum-possible-sampling-time/m-p/965439#M5442</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Markus,&lt;/P&gt;&lt;P&gt;You would need to prescale the ADC input clock,&lt;/P&gt;&lt;P&gt;in this case&amp;nbsp;SIRCDIV2_CLK&amp;nbsp;(SCG_SIRCDIV[SIRCDIV2]).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Daniel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 29 Oct 2019 09:17:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K116-ADC-Maximum-possible-sampling-time/m-p/965439#M5442</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2019-10-29T09:17:03Z</dc:date>
    </item>
  </channel>
</rss>

