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    <title>topic Re: int_sram_no_cacheable issue in S32K</title>
    <link>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2203171#M54385</link>
    <description>&lt;P&gt;hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/200831"&gt;@Julián_AragónM&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;&lt;P&gt;&amp;nbsp; 1. if I remove Det.c file from RTD i am getting compilation error. I no need Det related (det.c) file how to handle this problem?&lt;BR /&gt;&amp;nbsp; 2. if I took memory space from &lt;FONT color="#FF0000"&gt;int_sram&lt;/FONT&gt;. i am getting &lt;FONT color="#FF0000"&gt;HardFaulthandler&lt;/FONT&gt;. how to resolve this problem.?&lt;/P&gt;</description>
    <pubDate>Wed, 12 Nov 2025 04:15:59 GMT</pubDate>
    <dc:creator>dhanabharathi</dc:creator>
    <dc:date>2025-11-12T04:15:59Z</dc:date>
    <item>
      <title>int_sram_no_cacheable issue</title>
      <link>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2201885#M54320</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/61445"&gt;@nxp&lt;/a&gt;&amp;nbsp;,&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; I am using s32k31xevb and RTD 5.0 and i am configured ADC, CAN and PWM module, when I configure SPI module i am getting , '&lt;U&gt;&lt;EM&gt;non_cacheable_bss' will not fit in region 'int_sram_no_cacheable' error. region overflow by bytes 864.&lt;/EM&gt;&lt;/U&gt;&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; how to resolve this error? could you provide solution for this.&lt;/P&gt;</description>
      <pubDate>Mon, 10 Nov 2025 13:20:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2201885#M54320</guid>
      <dc:creator>dhanabharathi</dc:creator>
      <dc:date>2025-11-10T13:20:43Z</dc:date>
    </item>
    <item>
      <title>Re: int_sram_no_cacheable issue</title>
      <link>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2202057#M54336</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/253997"&gt;@dhanabharathi&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Size of this section is defined in the linker file.&lt;/P&gt;
&lt;P&gt;The int_sram_no_cacheable region is used for data that must stay consistent between the CPU and peripherals, such as DMA buffers. It avoids cache-related issues and ensures reliable memory access for real-time operations.&lt;/P&gt;
&lt;P&gt;You could&amp;nbsp;your linker file to allocate more space to the int_sram_no_cacheable region, however, you must make sure the new size does not overlap.&lt;/P&gt;
&lt;P&gt;Also, if you are not using the Det module, you can simply delete it from project source directory to free up some space:&amp;nbsp;&lt;A href="https://community.nxp.com/t5/S32M/S32DS-Update-RTD5-0-and-Compile-with-non-cacheable-bss-overflow/m-p/1993577" target="_blank"&gt;Solved: S32DS Update RTD5.0 and Compile with non_cacheable_bss overflow error - NXP Community&lt;/A&gt;.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;BR /&gt;Julián&lt;/P&gt;</description>
      <pubDate>Mon, 10 Nov 2025 18:14:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2202057#M54336</guid>
      <dc:creator>Julián_AragónM</dc:creator>
      <dc:date>2025-11-10T18:14:16Z</dc:date>
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    <item>
      <title>Re: int_sram_no_cacheable issue</title>
      <link>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2202467#M54356</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/200831"&gt;@Julián_AragónM&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;&lt;P&gt;&lt;FONT face="arial,helvetica,sans-serif"&gt;I have a couple of questions:&lt;/FONT&gt;&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;&lt;P&gt;&lt;FONT face="arial,helvetica,sans-serif"&gt;The scheduler manager and DET files are taking more memory. Is there any way to reduce the size of these scheduler manager files?&lt;/FONT&gt;&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;FONT face="arial,helvetica,sans-serif"&gt;For memory reallocation, is it possible to take additional size from &lt;STRONG&gt;&lt;FONT color="#c7254e"&gt;&lt;SPAN&gt;int_sram&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/STRONG&gt;? Will this cause any issues?&lt;/FONT&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 11 Nov 2025 07:11:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2202467#M54356</guid>
      <dc:creator>dhanabharathi</dc:creator>
      <dc:date>2025-11-11T07:11:19Z</dc:date>
    </item>
    <item>
      <title>Re: int_sram_no_cacheable issue</title>
      <link>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2202967#M54376</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/253997"&gt;@dhanabharathi&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;1. Yes. If you are not using default error tracer (DET), you can simply delete it. You can also reduce tasks/events or services in your scheduler/OS to reduce size.&lt;/P&gt;
&lt;P&gt;2. Yes. You can allocate extra space form int_sram, just ensure you do not overlap regions.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;BR /&gt;Julián&lt;/P&gt;</description>
      <pubDate>Tue, 11 Nov 2025 21:18:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2202967#M54376</guid>
      <dc:creator>Julián_AragónM</dc:creator>
      <dc:date>2025-11-11T21:18:50Z</dc:date>
    </item>
    <item>
      <title>Re: int_sram_no_cacheable issue</title>
      <link>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2203171#M54385</link>
      <description>&lt;P&gt;hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/200831"&gt;@Julián_AragónM&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;&lt;P&gt;&amp;nbsp; 1. if I remove Det.c file from RTD i am getting compilation error. I no need Det related (det.c) file how to handle this problem?&lt;BR /&gt;&amp;nbsp; 2. if I took memory space from &lt;FONT color="#FF0000"&gt;int_sram&lt;/FONT&gt;. i am getting &lt;FONT color="#FF0000"&gt;HardFaulthandler&lt;/FONT&gt;. how to resolve this problem.?&lt;/P&gt;</description>
      <pubDate>Wed, 12 Nov 2025 04:15:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2203171#M54385</guid>
      <dc:creator>dhanabharathi</dc:creator>
      <dc:date>2025-11-12T04:15:59Z</dc:date>
    </item>
    <item>
      <title>Re: int_sram_no_cacheable issue</title>
      <link>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2203960#M54418</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/253997"&gt;@dhanabharathi&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;1. Are you deleting all related Det files? Have you disabled all of the error detection in your modules? If not, the driver may try to include related files:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Snag_72e69c.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/365358i7FF22420370AA564/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Snag_72e69c.png" alt="Snag_72e69c.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Snag_73323c.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/365359iA7567FD15B1AC135/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Snag_73323c.png" alt="Snag_73323c.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;2. Hard to say without seeing what you modified or where does the hard fault happened, however, p&lt;SPAN&gt;lease check the .map file compiled by your project, and adjust the link file according to the size of your program.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;When adjusting the linker file, pay attention to MPU config and such. I suggest deleting Det.c for now to avoid overflow for now.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;BR /&gt;Julián&lt;/P&gt;</description>
      <pubDate>Wed, 12 Nov 2025 23:39:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2203960#M54418</guid>
      <dc:creator>Julián_AragónM</dc:creator>
      <dc:date>2025-11-12T23:39:59Z</dc:date>
    </item>
    <item>
      <title>Re: int_sram_no_cacheable issue</title>
      <link>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2204577#M54450</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/200831"&gt;@Julián_AragónM&lt;/a&gt;&amp;nbsp;,&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; I am adjusting the linker file like that attached blow. the memory region is not overlapped, but i am getting the hard fault handler issue, while MC_init_clock() function triggering. how resolve this problem?&amp;nbsp;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;if it is due to MPU problem, how to resolve this problem?&lt;/P&gt;&lt;P&gt;note: In my configuration MPU is disabled.&lt;/P&gt;</description>
      <pubDate>Thu, 13 Nov 2025 15:24:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2204577#M54450</guid>
      <dc:creator>dhanabharathi</dc:creator>
      <dc:date>2025-11-13T15:24:23Z</dc:date>
    </item>
    <item>
      <title>Re: int_sram_no_cacheable issue</title>
      <link>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2204659#M54457</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/253997"&gt;@dhanabharathi&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;It seems that the no cacheable area is not aligned on 4KB boundary.&lt;/P&gt;
&lt;P&gt;For now, could you try keeping the linker file the same, and simply deleting Det component to see if enough space is freed up? Have you disabled Det in the modules?&lt;/P&gt;
&lt;P&gt;int_sram_no_cacheable region should only be used to save specific data buffers of the modules such as MCL, SPI, etc.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards,&lt;BR /&gt;Julián&lt;/P&gt;</description>
      <pubDate>Thu, 13 Nov 2025 19:01:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2204659#M54457</guid>
      <dc:creator>Julián_AragónM</dc:creator>
      <dc:date>2025-11-13T19:01:31Z</dc:date>
    </item>
    <item>
      <title>Re: int_sram_no_cacheable issue</title>
      <link>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2204855#M54469</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/200831"&gt;@Julián_AragónM&lt;/a&gt;&amp;nbsp;,&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; I deleted Det related files still I need 4kb space in&amp;nbsp;&lt;SPAN&gt;int_sram_no_cacheable region.&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;could you give me aligned on 4KB boundary linker file or give me example for that.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 14 Nov 2025 04:26:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2204855#M54469</guid>
      <dc:creator>dhanabharathi</dc:creator>
      <dc:date>2025-11-14T04:26:07Z</dc:date>
    </item>
    <item>
      <title>Re: int_sram_no_cacheable issue</title>
      <link>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2205179#M54488</link>
      <description>&lt;P&gt;hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/200831"&gt;@Julián_AragónM&lt;/a&gt;&amp;nbsp;,&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp; &amp;nbsp;The linker file adjustment is correct, when I manually disable the &lt;FONT color="#FF0000"&gt;S32_MPU-&amp;gt;CTRL = 0,&amp;nbsp;&lt;FONT color="#000000"&gt;I am not getting hard fault error.&lt;BR /&gt;&amp;nbsp; &amp;nbsp;I am using S32 design studio 3.6.0 and RTD 5.0 version. how to solve this vis configuration. kindly provide solution for this problem.&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 14 Nov 2025 11:46:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2205179#M54488</guid>
      <dc:creator>dhanabharathi</dc:creator>
      <dc:date>2025-11-14T11:46:01Z</dc:date>
    </item>
    <item>
      <title>Re: int_sram_no_cacheable issue</title>
      <link>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2227960#M54693</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/253997"&gt;@dhanabharathi&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;MPU can be disabled with&amp;nbsp;&lt;SPAN&gt;Mpu_M7_Ip_Deinit().&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Also, most examples have MPU_ENABLED defined as a project symbol:&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Julin_AragnM_0-1763679199514.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/366699i3E851D70662FCBD5/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Julin_AragnM_0-1763679199514.png" alt="Julin_AragnM_0-1763679199514.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;This initializes the MPU inside&amp;nbsp;&lt;SPAN&gt;SystemInit() function at startup. Keep in mind this removes memory protection, you should update MPU regions to match your linker changes instead of disabling it.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;You can refer to ARM documentation:&lt;/SPAN&gt;&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;&lt;SPAN&gt;&lt;A href="https://developer.arm.com/documentation/ddi0403/latest/" target="_blank"&gt;ARMv7-M Architecture Reference Manual&lt;/A&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI&gt;&lt;SPAN&gt;&lt;A href="https://developer.arm.com/documentation/ddi0489/f/memory-protection-unit?lang=en" target="_self"&gt;Chapter 6. Memory Protection Unit&lt;/A&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI&gt;&lt;SPAN&gt;&lt;A href="https://developer.arm.com/documentation/dui0646/c/Cortex-M7-Peripherals/Optional-Memory-Protection-Unit" target="_self"&gt;Optional Memory Protection Unit&lt;/A&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;&lt;SPAN&gt;Best regards,&lt;BR /&gt;Julián&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 20 Nov 2025 22:57:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/int-sram-no-cacheable-issue/m-p/2227960#M54693</guid>
      <dc:creator>Julián_AragónM</dc:creator>
      <dc:date>2025-11-20T22:57:02Z</dc:date>
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