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    <title>S32K中的主题 How to Inject RAM and ROM Errors using EIM Module for NXP S32k312</title>
    <link>https://community.nxp.com/t5/S32K/How-to-Inject-RAM-and-ROM-Errors-using-EIM-Module-for-NXP/m-p/2193221#M53854</link>
    <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/37795"&gt;@lukaszadrapa&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;According to the NXP S32 Reference Manual, I followed the steps to inject a RAM error:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;&lt;P&gt;Enabled the &lt;STRONG&gt;SRAM0 channel&lt;/STRONG&gt;.&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;Configured the &lt;STRONG&gt;EICHD0_WORDm[CHKBIT_MASK]&lt;/STRONG&gt; and &lt;STRONG&gt;EICHD0_WORDm[Ba_bDATA_MASK]&lt;/STRONG&gt; fields for the channel used to inject the error.&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;Programmed the &lt;STRONG&gt;EICHEN&lt;/STRONG&gt; register to enable the corresponding injection channel.&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;Set the &lt;STRONG&gt;EIMCR[GEIEN]&lt;/STRONG&gt; bit to globally enable all configured error injection channels.&lt;/P&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;To create a &lt;STRONG&gt;multi-bit error&lt;/STRONG&gt;, I inverted two bits in either the &lt;STRONG&gt;CHKBIT_MASK&lt;/STRONG&gt; or &lt;STRONG&gt;DATA_MASK&lt;/STRONG&gt; fields of the &lt;STRONG&gt;EICHDn_WORD&lt;/STRONG&gt; registers.&lt;/P&gt;&lt;P&gt;After that, I configured the &lt;STRONG&gt;ERM (Error Reporting Module)&lt;/STRONG&gt; to monitor error status. However, when I checked the &lt;STRONG&gt;ERM_SR0&lt;/STRONG&gt; register after performing the multi-bit injection, I did not see any error status reported.&lt;/P&gt;&lt;P&gt;Could you please help me understand how to detect the multi-bit error status correctly? I have already enabled the ERM module clock. Is there anything else that needs to be configured?&lt;/P&gt;&lt;P&gt;Also, as per the reference manual, &lt;STRONG&gt;ECC is enabled by default for both RAM and ROM&lt;/STRONG&gt;. Is that correct?&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Note:&lt;/STRONG&gt; I don't want to use any external drivers like SPD or SAF for RAM checking&lt;/P&gt;&lt;P&gt;During startup i am performing SRAM memory initialization&lt;/P&gt;&lt;P&gt;Could u help how can i do RAM and ROM checks without Drivers (SPD and SAF)&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Anitha7_0-1761547021584.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/362619i14B7759EAE2E5237/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Anitha7_0-1761547021584.png" alt="Anitha7_0-1761547021584.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Anitha7_1-1761547635272.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/362620iC3E772F72D557642/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Anitha7_1-1761547635272.png" alt="Anitha7_1-1761547635272.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Mon, 27 Oct 2025 06:47:58 GMT</pubDate>
    <dc:creator>Anitha7</dc:creator>
    <dc:date>2025-10-27T06:47:58Z</dc:date>
    <item>
      <title>How to Inject RAM and ROM Errors using EIM Module for NXP S32k312</title>
      <link>https://community.nxp.com/t5/S32K/How-to-Inject-RAM-and-ROM-Errors-using-EIM-Module-for-NXP/m-p/2193221#M53854</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/37795"&gt;@lukaszadrapa&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;According to the NXP S32 Reference Manual, I followed the steps to inject a RAM error:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;&lt;P&gt;Enabled the &lt;STRONG&gt;SRAM0 channel&lt;/STRONG&gt;.&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;Configured the &lt;STRONG&gt;EICHD0_WORDm[CHKBIT_MASK]&lt;/STRONG&gt; and &lt;STRONG&gt;EICHD0_WORDm[Ba_bDATA_MASK]&lt;/STRONG&gt; fields for the channel used to inject the error.&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;Programmed the &lt;STRONG&gt;EICHEN&lt;/STRONG&gt; register to enable the corresponding injection channel.&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;Set the &lt;STRONG&gt;EIMCR[GEIEN]&lt;/STRONG&gt; bit to globally enable all configured error injection channels.&lt;/P&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;To create a &lt;STRONG&gt;multi-bit error&lt;/STRONG&gt;, I inverted two bits in either the &lt;STRONG&gt;CHKBIT_MASK&lt;/STRONG&gt; or &lt;STRONG&gt;DATA_MASK&lt;/STRONG&gt; fields of the &lt;STRONG&gt;EICHDn_WORD&lt;/STRONG&gt; registers.&lt;/P&gt;&lt;P&gt;After that, I configured the &lt;STRONG&gt;ERM (Error Reporting Module)&lt;/STRONG&gt; to monitor error status. However, when I checked the &lt;STRONG&gt;ERM_SR0&lt;/STRONG&gt; register after performing the multi-bit injection, I did not see any error status reported.&lt;/P&gt;&lt;P&gt;Could you please help me understand how to detect the multi-bit error status correctly? I have already enabled the ERM module clock. Is there anything else that needs to be configured?&lt;/P&gt;&lt;P&gt;Also, as per the reference manual, &lt;STRONG&gt;ECC is enabled by default for both RAM and ROM&lt;/STRONG&gt;. Is that correct?&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Note:&lt;/STRONG&gt; I don't want to use any external drivers like SPD or SAF for RAM checking&lt;/P&gt;&lt;P&gt;During startup i am performing SRAM memory initialization&lt;/P&gt;&lt;P&gt;Could u help how can i do RAM and ROM checks without Drivers (SPD and SAF)&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Anitha7_0-1761547021584.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/362619i14B7759EAE2E5237/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Anitha7_0-1761547021584.png" alt="Anitha7_0-1761547021584.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Anitha7_1-1761547635272.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/362620iC3E772F72D557642/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Anitha7_1-1761547635272.png" alt="Anitha7_1-1761547635272.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 27 Oct 2025 06:47:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/How-to-Inject-RAM-and-ROM-Errors-using-EIM-Module-for-NXP/m-p/2193221#M53854</guid>
      <dc:creator>Anitha7</dc:creator>
      <dc:date>2025-10-27T06:47:58Z</dc:date>
    </item>
    <item>
      <title>Re: How to Inject RAM and ROM Errors using EIM Module for NXP S32k312</title>
      <link>https://community.nxp.com/t5/S32K/How-to-Inject-RAM-and-ROM-Errors-using-EIM-Module-for-NXP/m-p/2193536#M53881</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/228025"&gt;@Anitha7&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Here is a simple example that injects double-bit ECC fault into DTCM on S32K344.&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-EIM-ERM-DTCM-Baremetal-v2-0-S32DS36/ta-p/2193534" target="_blank" rel="noopener"&gt;https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-EIM-ERM-DTCM-Baremetal-v2-0-S32DS36/ta-p/2193534&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Daniel&lt;/P&gt;</description>
      <pubDate>Mon, 27 Oct 2025 13:56:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/How-to-Inject-RAM-and-ROM-Errors-using-EIM-Module-for-NXP/m-p/2193536#M53881</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2025-10-27T13:56:44Z</dc:date>
    </item>
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