EMIOS sysncarations

Ayaz — Tue, 07 Oct 2025 16:47:14 GMT

Hi,
I’ve designed a motor control system using a motor driver that has two inputs: IN1 and IN2. Here's how the system works:

IN1 is always high, so the motor continuously rotates forward.
IN2 is modulated using eMIOS_0_CH15, which allows me to control the current flowing through the motor.
When both IN1 and IN2 are high, the motor enters slow decay mode.
When IN2 is low, current actively flows through the motor — this is the phase I want to measure.

To ensure accurate current measurement, I’ve configured eMIOS_0_CH15 with active-low polarity, so the signal starts low. This way, the current flows during the low phase, and I can sample the ADC at the beginning of the PWM period when current starts flowing.

ADC Trigger Setup:

I’ve configured eMIOS_0_CH1 in OPWMT mode to trigger the ADC.
Both eMIOS_0_CH1 and eMIOS_0_CH15 share the same timebase (eMIOS_0_CH23) and period.
The minimum duty cycle where current can be reliably measured is 4%.

The Issue:

Even though both channels share the same timebase and period, the flag generation from eMIOS_0_CH1 occurs ~2 µs later than the start of the PWM signal on eMIOS_0_CH15. This misalignment causes the ADC to sample before current starts flowing, which is not desired.

I’ve created an example project to help debug this issue. I’d appreciate your help in identifying the cause and finding a solution to ensure the ADC trigger aligns precisely with the start of the current flow.

S32k344
RTD:6.0.0

Re: EMIOS sysncarations

_Leo_ — Wed, 08 Oct 2025 21:12:26 GMT

Thank you for your interest in our products and for contributing to our community.

Flag for OPWMT is generated based in Trigger parameter (for your case at tick 0).

The delay of ~2us is the time that takes to the MCU to enter to the interrupt and toggle a pin. The issue is that PWM period is too fast.

It can even be seen that the time to toggle a pin twice is considerable with respect to the established PWM period.

The workaround that I can propose to you, is to phase shift the OPWMB signal to match the trigger into the low time period. A phase shift of 50 ticks look like this:

But I recommend you set the phase shift value empirically according to your needs.

We hope this resolves your issue.

topic EMIOS sysncarations in S32K

EMIOS sysncarations

ADC Trigger Setup:

The Issue:

Re: EMIOS sysncarations