<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>S32K中的主题 Re: HW CRC slow?</title>
    <link>https://community.nxp.com/t5/S32K/HW-CRC-slow/m-p/957201#M5322</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Daniel,&amp;nbsp;&lt;/P&gt;&lt;P&gt;I tried using DMA, here some results on 128 KB&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;TABLE width="273"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD width="81"&gt;clock (MHz)&lt;/TD&gt;&lt;TD width="64"&gt;cpu&lt;/TD&gt;&lt;TD width="64"&gt;dma&lt;/TD&gt;&lt;TD width="64"&gt;ratio&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;24&lt;/TD&gt;&lt;TD&gt;8&lt;/TD&gt;&lt;TD&gt;5.5&lt;/TD&gt;&lt;TD&gt;0.6875&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;48&lt;/TD&gt;&lt;TD&gt;13.5&lt;/TD&gt;&lt;TD&gt;6.9&lt;/TD&gt;&lt;TD&gt;0.511111&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;On a CM4 with the same clock speed shall I expect the same results, or due to the&amp;nbsp;Harvard architecture I can expect a significative improvement in the DMA scenario?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 11 Sep 2019 09:20:53 GMT</pubDate>
    <dc:creator>Catosh</dc:creator>
    <dc:date>2019-09-11T09:20:53Z</dc:date>
    <item>
      <title>HW CRC slow?</title>
      <link>https://community.nxp.com/t5/S32K/HW-CRC-slow/m-p/957199#M5320</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&amp;nbsp;&lt;/P&gt;&lt;P&gt;Are there any benchmark reports about CRC peripheral speed and performances on the S32K11x mcu?&lt;/P&gt;&lt;P&gt;I need to check the integrity of the whole flash memory at the startup and in my opinion it takes *a lot* of time.&lt;/P&gt;&lt;P&gt;At 24MHz core speed with 32bit writes instead of 8 I measure 15ms for 128KB of memory.&lt;/P&gt;&lt;P&gt;I am using the core to load data; i can imagine that DMA could speed up computation but I don't know how much.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Any suggestions or best practices to speed up the crc computation?&amp;nbsp;&lt;/P&gt;&lt;P&gt;K.R.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 06 Sep 2019 07:55:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/HW-CRC-slow/m-p/957199#M5320</guid>
      <dc:creator>Catosh</dc:creator>
      <dc:date>2019-09-06T07:55:07Z</dc:date>
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    <item>
      <title>Re: HW CRC slow?</title>
      <link>https://community.nxp.com/t5/S32K/HW-CRC-slow/m-p/957200#M5321</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/Catosh"&gt;Catosh&lt;/A&gt;,&lt;/P&gt;&lt;P&gt;I would try&amp;nbsp;using DMA.&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-332223"&gt;Example MPC5748G CRC32 GHS614&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;There's the same DMA module, so you can take a look at how to configure the DMA.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;BR /&gt;Daniel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Sep 2019 08:02:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/HW-CRC-slow/m-p/957200#M5321</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2019-09-11T08:02:19Z</dc:date>
    </item>
    <item>
      <title>Re: HW CRC slow?</title>
      <link>https://community.nxp.com/t5/S32K/HW-CRC-slow/m-p/957201#M5322</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Daniel,&amp;nbsp;&lt;/P&gt;&lt;P&gt;I tried using DMA, here some results on 128 KB&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;TABLE width="273"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD width="81"&gt;clock (MHz)&lt;/TD&gt;&lt;TD width="64"&gt;cpu&lt;/TD&gt;&lt;TD width="64"&gt;dma&lt;/TD&gt;&lt;TD width="64"&gt;ratio&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;24&lt;/TD&gt;&lt;TD&gt;8&lt;/TD&gt;&lt;TD&gt;5.5&lt;/TD&gt;&lt;TD&gt;0.6875&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;48&lt;/TD&gt;&lt;TD&gt;13.5&lt;/TD&gt;&lt;TD&gt;6.9&lt;/TD&gt;&lt;TD&gt;0.511111&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;On a CM4 with the same clock speed shall I expect the same results, or due to the&amp;nbsp;Harvard architecture I can expect a significative improvement in the DMA scenario?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Sep 2019 09:20:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/HW-CRC-slow/m-p/957201#M5322</guid>
      <dc:creator>Catosh</dc:creator>
      <dc:date>2019-09-11T09:20:53Z</dc:date>
    </item>
    <item>
      <title>Re: HW CRC slow?</title>
      <link>https://community.nxp.com/t5/S32K/HW-CRC-slow/m-p/957202#M5323</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes, I would expect some improvement but it depends on code executed on CM4 (on traffic on crossbar). The best option is to test it. There's also advantage of higher system clock on S32K14x.&lt;/P&gt;&lt;P&gt;By the way, if core is used (not DMA) then executing from RAM should help on S32K11x. It will have similar effect like enabling cache on CM4.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Lukas&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 13 Sep 2019 07:24:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/HW-CRC-slow/m-p/957202#M5323</guid>
      <dc:creator>lukaszadrapa</dc:creator>
      <dc:date>2019-09-13T07:24:49Z</dc:date>
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  </channel>
</rss>

