topic Re: Re S32K146 Transmit Delay in S32K

S32K146 Transmit Delay

Kofi_Wang1 — Wed, 10 Sep 2025 02:53:45 GMT

Hello

We are developing the bootloader software base on S32K146 MCU with CANFD communication. But we encounter an issue which really confuzed us, that is ECU transmit the message with a flexible delay, some times it transmit the positive response onto CAN bus within 1ms after receiving the request from test, some times those delay is really 'big' which is neally 224ms which exceeds the CAN_TP transmit timer limit(As). Could some one please help me fix this issue?

Information about our ECU is shown as below and also the attached picture:

1. 2 MB should be used to recceive 2 messages(ID: 0x714 for physical address, ID: 0x7DF for functional address );

2. 1 MB should be used to transmit 1 messgae(ID:0x794)

3. CANFD arbitration baudrate is 500K/s while data field baudrate is 2MB/s

4. Frame DLC is 64 bytes.

5. We don't use interrupt to receive or transmit in our bootloader software, but use polling type insteadlly.

6. Our Transceiver is TLE9263

7. Our CAN Clocksource is SYS_CLK(80MHZ)

8. I put a monitor point in Can_write function just before writing the MB. and measure the duration bewteen the monitor point and the message was transmitted onto CANTx PIN using logic analyzer, the result is that: it will take nearly 223.95ms to transmit the positve response onto CAN Tx PIN after writing the MB.(Please refer to the attached picture ).

It seems that this huge delay is not raised from arbitration because total MB used is only 7, and there is no other node in CAN loop except our ECU and Tester(CANOE VIN1640)

My CAN_init() function posted as below:

void Can_Init(void)
{
/**
* GPIO
* CAN_RX U4_9_CAN0_RX PE4 ALT5
* CAN_TX U4_8_CAN0_TX PE5 ALT5
*/
PORTE->PCR[4] = PORT_PCR_MUX(5);
PORTE->PCR[5] = PORT_PCR_MUX(5);

#if CAN_FD == CAN_FD_TYPE_EN
uint32_t i = 0;
uint32_t tempECR;
uint32_t WaitCounter = 0;

/* Clock */
PCC->PCCn[PCC_FlexCAN0_INDEX] |= PCC_PCCn_CGC_MASK; /* CGC=1: enable clock to FlexCAN0 */

/* CAN */
CAN0->MCR |= CAN_MCR_SOFTRST_MASK;
CAN0->MCR |= CAN_MCR_MDIS_MASK; /* MDIS=1: Disable module before selecting clock */
WaitCounter = 0;
while(!((CAN0->MCR & CAN_MCR_SOFTRST_MASK) >> CAN_MCR_SOFTRST_SHIFT)) {WaitCounter++;}

CAN0->IMASK1 = 0x00000000ul;
CAN0->ESR1 &= ~CAN_ESR1_BOFFINT_MASK;

CAN0->CTRL1 |= (CAN_CTRL1_CLKSRC(1) /* CLKsrc=1: Clock Source = SYS_CLK (80 MHz) */
|CAN_CTRL1_BOFFMSK(0) /* Busoff interrupt enable */
|CAN_CTRL1_BOFFREC(0)); /* Busoff auto recovery enable. */

CAN0->MCR &= ~CAN_MCR_MDIS_MASK; /* MDIS=0; Enable module config. (Sets FRZ, HALT)*/
CAN0->MCR |= (CAN_MCR_FRZ_MASK | CAN_MCR_HALT_MASK);

WaitCounter = 0;
while(!((CAN0->MCR & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT)) {WaitCounter++;}

/* Good practice: wait for FRZACK=1 on freeze mode entry/exit */
tempECR = CAN0->ECR;
CAN0->ECR = 0x00000000UL;
tempECR = tempECR;

/* Configure nominal phase: 500 KHz bit time, 80 MHz Sclock */
CAN0->CBT = CAN_CBT_BTF(1) /* Bit time define enable. */
|CAN_CBT_EPRESDIV(1) /* EPRESDIV = Prescaler + 1 = 2 */
|CAN_CBT_EPSEG2(15) /* EPSEG2 = 15 */
|CAN_CBT_EPSEG1(15) /* EPSEG1 = 15 */
|CAN_CBT_EPROPSEG(46)/* EPROPSEG = 46 */
|CAN_CBT_ERJW(15);/* ERJW = 15 */

/* BITRATEn =Fcanclk /( [(1 + (EPSEG1+1) + (EPSEG2+1) + (EPROPSEG + 1)] x (EPRESDIV+1))
= 80 MHz /( [(1 + ( 15 +1) + ( 15 +1) + ( 46 + 1)] x ( 1 +1))
= 80 MHz /( [1+16+16+47] x 2) = 80 MHz /(80x2) = 500 Kz

Sample Point = (3 + PSEG1 + PROPSEG) /(4+ PSEG1 + PSEG2 + PROPSEG)
(17 + 15 + 46) /(18 + 15 + 15 + 46) = 80% */

/* Configure data phase: 2 MHz bit time, 80 MHz Sclock */
CAN0->FDCBT = CAN_CBT_EPSEG2(3) /* FPSEG2 = 3 */
|CAN_CBT_EPSEG1(7) /* EPSEG1 = 7 */
|CAN_CBT_EPROPSEG(7) /* FPROPSEG = 7 */
|CAN_CBT_ERJW(3) /* FRJW = 3 */
|CAN_FDCBT_FPRESDIV(1);/* FPRESDIV = Prescaler + 1 = 2 */

/* BITRATEf = Fcanclk /( [(1 + (FPSEG1+1) + (FPSEG2+1) + (FPROPSEG)] x (FPRESDIV+1))
= 80 MHz /( [(1 + ( 7 +1) + ( 3 +1) + ( 7 )] x ( 1 +1))
= 80 MHz /( [1+8+4+7] x 2) = 80 MHz /(20x2) = 80 MHz / 40 = 2 MHz
Sample Point = (2 + PSEG1 + PROPSEG) /(3 + PSEG1 + PSEG2 + PROPSEG)
(4+ 7 + 7) /(5 + 7 + 3 + 7) = 80% */

CAN0->FDCTRL = CAN_FDCTRL_FDRATE(1) /* BRS=1: enable Bit Rate Swtich in frame's header, Configure bit rate switch, data size, transcv'r delay */
|CAN_FDCTRL_MBDSR0(3) /* MBDSR0=3: Region 0 has 64bytes data in frame's payload, 7Mb */
|CAN_FDCTRL_TDCEN(1) /* MBDSR1: Not applicable */
|CAN_FDCTRL_TDCOFF(31); /* Transceiver Delay Compensation Offset 15 */

/* PRIO = 0: CANFD is used, Enable CRC fix for ISO CAN FD */
CAN0->CTRL2 |= CAN_CTRL2_TASD(30) | CAN_CTRL2_ISOCANFDEN(1);

/* TDCEN=1: enable Transceiver Delay Compensation */
/* TDCOFF=5: 5 CAN clocks (300us) offset used */

for(i = 0; i < 128u; i++)
{
/* CAN0: clear 128 words RAM in FlexCAN 0
Clear msg buf words. All buffers CODE=0 (inactive) */
CAN0->RAMn[i] = 0;
}

for(i=0; i < 16u; i++ )
{
/* In FRZ mode, init CAN0 16 msg buf filters
Check all ID bits for incoming messages*/
CAN0->RXIMR[i] = 0x1ffffffful;
}

/* Global acceptance mask: check all ID bits */
CAN0->RXMGMASK = 0xFFFFFFFFul;
CAN0->RX14MASK = 0xFFFFFFFFul;
CAN0->RX15MASK = 0xFFFFFFFFul;

/* Message Buffer 0 - receive setup: */
/* Msg Buf 0, word 0: Enable for reception */
/* EDL = 1: Extended Data Length for CAN FD */
/* BRS = 1: Bit Rate Switch enabled */
/* ESI = 0: Error state */
/* CODE = 4: MB set to RX inactive */
/* IDE = 0: Standard ID */
/* SRR, RTR, TIME STAMP = 0: not applicable */

CAN0->RAMn[0 * CAN_MSG_BUF_SIZE + 0] = CAN_RAMn_EDL(1) +
CAN_RAMn_BRS(1) +
CAN_RAMn_ESI(0) +
CAN_RAMn_CODE(CAN_MSG_BUF_RX_EMPTY) +
CAN_RAMn_IDE(0) +
CAN_RAMn_SRR(0) +
CAN_RAMn_RTR(0);

CAN0->RAMn[0 * CAN_MSG_BUF_SIZE + 1] = ((uint32_t)ID_REQUEST_PHY) << 18u;
// CAN0->RXIMR[0] = (((uint32_t)(~(ID_REQUEST_PHY ^ ID_REQUEST_FUN))) << 18u) & 0x1ffffffful;
CAN0->RXIMR[0] = 0x1ffffffful;
CAN0->RAMn[1 * CAN_MSG_BUF_SIZE + 0] = CAN_RAMn_EDL(1) +
CAN_RAMn_BRS(1) +
CAN_RAMn_ESI(0) +
CAN_RAMn_CODE(CAN_MSG_BUF_RX_EMPTY) +
CAN_RAMn_IDE(0) +
CAN_RAMn_SRR(0) +
CAN_RAMn_RTR(0);

CAN0->RAMn[1 * CAN_MSG_BUF_SIZE + 1] = ((uint32_t)ID_REQUEST_FUN) << 18u;
CAN0->RXIMR[1] = 0x1ffffffful;

CAN0->MCR = 0x00030806ul; /* Negate FlexCAN 0 halt state & enable CAN FD for 7 MBs */

gs_CanControllerStatus[0] = CAN_STATUS_IDLE;
WaitCounter = 0;
while ((CAN0->MCR & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT){WaitCounter++;}
/* Good practice: wait for FRZACK to clear (not in freeze mode) */
WaitCounter = 0;
while ((CAN0->MCR & CAN_MCR_NOTRDY_MASK) >> CAN_MCR_NOTRDY_SHIFT){WaitCounter++;}
}

And My Can_write()function posted as below:
bl_Error_t Can_Write(bl_CanHandle_t handle, const bl_Buffer_t *buffer, bl_Size_t size)
{
#if CAN_FD == CAN_FD_TYPE_EN
bl_Error_t ret = BL_ERR_NOT_OK;
uint32_t Can_ID = 0x0;
uint8_t Tx_handle = 0;
uint8_t dlc;
CAN_message_t msg_tx;

dlc = Can__SizeToDlc(size);

if (handle > CAN_TXHANDLE_NUM)
{
return ret;
}
Tx_handle = g_CanTxHandleCfg[handle].controller;

if (gs_CanControllerStatus[Tx_handle] != CAN_STATUS_IDLE)
{
ret = BL_ERR_CAN_BUSY;
return ret;
}
Can_ID = g_CanTxHandleCfg[handle].id << 18;

do
{
for (uint8_t i = 0; i < CAN_MAX_NUMBER_OF_CONTROLLER; i++)
{
if (gs_CanControllerCfg[i].usage == CAN_CONTROLLER_UNUSED)
{
continue;
}

if ( (Tx_handle == gs_CanControllerCfg[i].phyId)
&& (CAN_STATUS_IDLE == gs_CanControllerStatus[i]))
{
msg_tx.id = Can_ID;
Can__CopyData(msg_tx.data.bytes,buffer,size);
msg_tx.length = dlc;
TLE9261_Write(0x40, 0x5F);/*This is software monitor point which I put here*/
S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 17] = SWAP_UINT32(msg_tx.data.longs[15]);//((uint32_t)buffer[60]) << 24 | ((uint32_t)buffer[61]) << 16 | ((uint32_t)buffer[62]) << 8 | ((uint32_t)buffer[63]);
S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 16] = SWAP_UINT32(msg_tx.data.longs[14]);//((uint32_t)buffer[56]) << 24 | ((uint32_t)buffer[57]) << 16 | ((uint32_t)buffer[58]) << 8 | ((uint32_t)buffer[59]);
S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 15] = SWAP_UINT32(msg_tx.data.longs[13]);//((uint32_t)buffer[52]) << 24 | ((uint32_t)buffer[53]) << 16 | ((uint32_t)buffer[53]) << 8 | ((uint32_t)buffer[55]);
S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 14] = SWAP_UINT32(msg_tx.data.longs[12]);//((uint32_t)buffer[48]) << 24 | ((uint32_t)buffer[49]) << 16 | ((uint32_t)buffer[50]) << 8 | ((uint32_t)buffer[51]);
S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 13] = SWAP_UINT32(msg_tx.data.longs[11]);//((uint32_t)buffer[44]) << 24 | ((uint32_t)buffer[45]) << 16 | ((uint32_t)buffer[46]) << 8 | ((uint32_t)buffer[47]);
S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 12] = SWAP_UINT32(msg_tx.data.longs[10]);//((uint32_t)buffer[40]) << 24 | ((uint32_t)buffer[41]) << 16 | ((uint32_t)buffer[42]) << 8 | ((uint32_t)buffer[43]);
S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 11] = SWAP_UINT32(msg_tx.data.longs[9]);//((uint32_t)buffer[36]) << 24 | ((uint32_t)buffer[37]) << 16 | ((uint32_t)buffer[38]) << 8 | ((uint32_t)buffer[39]);
S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 10] = SWAP_UINT32(msg_tx.data.longs[8]);//((uint32_t)buffer[32]) << 24 | ((uint32_t)buffer[33]) << 16 | ((uint32_t)buffer[34]) << 8 | ((uint32_t)buffer[35]);
S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 9] = SWAP_UINT32(msg_tx.data.longs[7]);//((uint32_t)buffer[28]) << 24 | ((uint32_t)buffer[29]) << 16 | ((uint32_t)buffer[30]) << 8 | ((uint32_t)buffer[31]);
S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 8] = SWAP_UINT32(msg_tx.data.longs[6]);//((uint32_t)buffer[24]) << 24 | ((uint32_t)buffer[25]) << 16 | ((uint32_t)buffer[26]) << 8 | ((uint32_t)buffer[27]);
S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 7] = SWAP_UINT32(msg_tx.data.longs[5]);//((uint32_t)buffer[20]) << 24 | ((uint32_t)buffer[21]) << 16 | ((uint32_t)buffer[22]) << 8 | ((uint32_t)buffer[23]);
S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 6] = SWAP_UINT32(msg_tx.data.longs[4]);//((uint32_t)buffer[16]) << 24 | ((uint32_t)buffer[17]) << 16 | ((uint32_t)buffer[18]) << 8 | ((uint32_t)buffer[19]);
S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 5] = SWAP_UINT32(msg_tx.data.longs[3]);//((uint32_t)buffer[12]) << 24 | ((uint32_t)buffer[13]) << 16 | ((uint32_t)buffer[14]) << 8 | ((uint32_t)buffer[15]);
S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 4] = SWAP_UINT32(msg_tx.data.longs[2]);//((uint32_t)buffer[8]) << 24 | ((uint32_t)buffer[9]) << 16 | ((uint32_t)buffer[10]) << 8 | ((uint32_t)buffer[11]);
S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 3] = SWAP_UINT32(msg_tx.data.longs[1]);//((uint32_t)buffer[4]) << 24 | ((uint32_t)buffer[5]) << 16 | ((uint32_t)buffer[6]) << 8 | ((uint32_t)buffer[7]);
S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 2] = SWAP_UINT32(msg_tx.data.longs[0]);//((uint32_t)buffer[0]) << 24 | ((uint32_t)buffer[1]) << 16 | ((uint32_t)buffer[2]) << 8 | ((uint32_t)buffer[3]);
S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 1] = Can_ID; /* MB8 word 1: Tx msg with given ID */
S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 0] = CAN_RAMn_EDL(1) /* EDL=1 CAN FD format frame*/
|CAN_RAMn_BRS(1) /* BRS=1: Bit rate is switched inside msg */
|CAN_RAMn_ESI(0) /* ESI=0: ??? */
|CAN_RAMn_CODE(CAN_TX_MB_CODE_TRANS) /* CODE=0xC: Activate msg buf to transmit */
|CAN_RAMn_SRR(0) /* SRR=1 Tx frame (not req'd for std ID) */
|CAN_RAMn_IDE(0) /* IDE=0: Standard ID */
|CAN_RAMn_RTR(0) /* RTR = 0: data, not remote tx request frame*/
|CAN_RAMn_DLC(dlc); /* DLC=x; 1,2,3,4,5,6,7,8, 9-12,10-16, 11-20, 12-24, 13-32, 14-48, 15-64bytes */

// while (!(S32K_CAN(Tx_handle).IFLAG1 & 0x100)) {}; /* Wait for CAN 0 MB 8 flag */
// S32K_CAN(Tx_handle).IFLAG1 = 0x00000100; /* Clear CAN 0 MB 8 flag without clearing others*/
gs_CanControllerStatus[i] = CAN_STATUS_TRANSMITTING;
ret = BL_ERR_OK;
}
}
} while(0);

return ret;

}

Re: S32K146 Transmit Delay

PetrS — Wed, 10 Sep 2025 10:48:42 GMT

Hi,

your CAN init looks normal. Only TDC is not needed at 2Mbit at all, anyway TDCOFF looks configured properly. You can try to keep default TASD value as well, but I do not expect difference.
So from description just single MB is used for transmission, from your code it is CAN_USED_HRH_NUM (value?). If this message buffer CS word is written, the MB starts to participate in arbitration process, should be selected as winner and moved out to TX SMB waiting for first opportunity on the bus to be really transmitted. Here the delay can appear due to bus arbitration, if there is any other message on the bus with lower ID. So check that, you wrote no other node is connected but one of RX message has higher arbitration value (lower ID).
Another source of delay could be the code itself. There is some code between TLE9261_Write and CAN_USED_HRH_NUM MB CS word writing. Are you sure this cannot be interrupted by other code/task, so adding more SW delay here?
Also error detected during transmission will delay actual transmit, but you can see wrong message and error messages on the bus/can tool.

BR, Petr

Re: S32K146 Transmit Delay

Kofi_Wang1 — Wed, 10 Sep 2025 11:34:24 GMT

Hello PetrS

Thank you so much for your kind reply. Let me clarify some points first.

1. For TDCOFF, I refer to the RF manual and calculate it using the parameters which is defined in customer CAN Spec, so I think it is OK here.

2. In my code, MB0 used to receive physical address ID(0x714) message, MB1 used to receive function address ID(0x7DF)message; MB2-MB5 is reserved, MB6 is used for transmit. Since S32K146 Flex CAN0 has 7 MBs for those messages with payload 64 bytes, so CAN_USED_HRH_NUM in my code is 6.

3. For the bus arbitration, I understand what you mean, and sorry for missing some snapshot from my picture. I added them here, please refer to them in the attachment. There is only 1 node in my test bench, that is my ECU, no other node to arbitrate with my ECU except the tester(Vector CANOE VIN1640). In order to wake my ECU after finishing the flashing, I send a NM message with 100ms period. So from my point of view, this delay should not due to the bus arbitration.

4. In order to capture where the delay happens, I put a monitor point in my code, that is TLE9261_Write (which you also mentioned in your reply). By doing this, I can capture the SPI signal which is triggered by calling TLE9261_Write(), This is names measurement start point in my logic analyzer project, which means this point is just before transmitting the message(write data into the transmitting MB also update the CS code of the MB); And I also measure the data in CANRx and CANTx PIN; By doing this, I find the delay between I call TLE9261_Write()and the message was transmitted onto the CAN Tx PIN is nearlly 223ms!!! That is really long. You can see my measurement result in the attachments.

5. So I guess the delay may com from the code between TLE9261_Write and CAN_USED_HRH_NUM MB CS word writing, just as you saied in your reply. But the only interrupts I used in my bootloader code is system tick which I use it to count time and hardfault, which I use it to cope with some fault scenarios. This should not cause so big delay I think.

So could you please check these information again and help me to figure out where the delay come from?

Thank you so much.

Re: S32K146 Transmit Delay

PetrS — Thu, 11 Sep 2025 12:10:37 GMT

Hi,

so from MeasurementStartPoint,jpg I see 0x714 message is received, after cca 150us 0x5FC0 is sent on SPI SOUT, is this frame equivalent to TLE9261_Write(0x40,0x5F) used in code?
Do you have a zoom on stop time when TX message is sent?
Are you able to get screenshots for normal response (within 1ms)?
What is periodic (30us) SPI transfer between CAN messages? How this is handled in code?

If you want to test the code between TLE9261_Write(0x40,0x5F) and MB6 CS word writing is not interrupted, simply disable/enable interrupts before/after.

BR, Petr

Re S32K146 Transmit Delay

Kofi_Wang1 — Fri, 12 Sep 2025 13:25:53 GMT

Hello

thank you so much for your reply. I'd like to answer your first question which I quoted here "so from MeasurementStartPoint,jpg I see 0x714 message is received, after cca 150us 0x5FC0 is sent on SPI SOUT, is this frame equivalent to TLE9261_Write(0x40,0x5F) used in code?"

yes , it is equivalent to TLE9261_Write(0x40,0x5F) used in code.

For the measurement stop point, I introduced another 2 TLE9261_Write(0x40,0x5F) function in my code, you can see them in attached picture named 'Monitor point', I also post my code here:

bl_Error_t Can_Write(bl_CanHandle_t handle, const bl_Buffer_t *buffer, bl_Size_t size)

{

bl_Error_t ret = BL_ERR_NOT_OK;

uint32_t Can_ID = 0x0;

uint8_t Tx_handle = 0;

uint8_t dlc;

CAN_message_t msg_tx;

dlc = Can__SizeToDlc(size);

if (handle > CAN_TXHANDLE_NUM)

{

return ret;

}

Tx_handle = g_CanTxHandleCfg[handle].controller;

if (gs_CanControllerStatus[Tx_handle] != CAN_STATUS_IDLE)

{

ret = BL_ERR_CAN_BUSY;

return ret;

}

Can_ID = g_CanTxHandleCfg[handle].id << 18;

{

for (uint8_t i = 0; i < CAN_MAX_NUMBER_OF_CONTROLLER; i++)

{

if (gs_CanControllerCfg[i].usage == CAN_CONTROLLER_UNUSED)

{

continue;

}

if ( (Tx_handle == gs_CanControllerCfg[i].phyId)

&& (CAN_STATUS_IDLE == gs_CanControllerStatus[i]))

{

msg_tx.id = Can_ID;

Can__CopyData(msg_tx.data.bytes,buffer,size);

msg_tx.length = dlc;

TLE9261_Write(0x40, 0x5F);/*Monitor Point 1*/

S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 17] = SWAP_UINT32(msg_tx.data.longs[15]);//((uint32_t)buffer[60]) << 24 | ((uint32_t)buffer[61]) << 16 | ((uint32_t)buffer[62]) << 8 | ((uint32_t)buffer[63]);

S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 16] = SWAP_UINT32(msg_tx.data.longs[14]);//((uint32_t)buffer[56]) << 24 | ((uint32_t)buffer[57]) << 16 | ((uint32_t)buffer[58]) << 8 | ((uint32_t)buffer[59]);

S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 15] = SWAP_UINT32(msg_tx.data.longs[13]);//((uint32_t)buffer[52]) << 24 | ((uint32_t)buffer[53]) << 16 | ((uint32_t)buffer[53]) << 8 | ((uint32_t)buffer[55]);

S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 14] = SWAP_UINT32(msg_tx.data.longs[12]);//((uint32_t)buffer[48]) << 24 | ((uint32_t)buffer[49]) << 16 | ((uint32_t)buffer[50]) << 8 | ((uint32_t)buffer[51]);

S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 13] = SWAP_UINT32(msg_tx.data.longs[11]);//((uint32_t)buffer[44]) << 24 | ((uint32_t)buffer[45]) << 16 | ((uint32_t)buffer[46]) << 8 | ((uint32_t)buffer[47]);

S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 12] = SWAP_UINT32(msg_tx.data.longs[10]);//((uint32_t)buffer[40]) << 24 | ((uint32_t)buffer[41]) << 16 | ((uint32_t)buffer[42]) << 8 | ((uint32_t)buffer[43]);

S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 11] = SWAP_UINT32(msg_tx.data.longs[9]);//((uint32_t)buffer[36]) << 24 | ((uint32_t)buffer[37]) << 16 | ((uint32_t)buffer[38]) << 8 | ((uint32_t)buffer[39]);

S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 10] = SWAP_UINT32(msg_tx.data.longs[8]);//((uint32_t)buffer[32]) << 24 | ((uint32_t)buffer[33]) << 16 | ((uint32_t)buffer[34]) << 8 | ((uint32_t)buffer[35]);

S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 9] = SWAP_UINT32(msg_tx.data.longs[7]);//((uint32_t)buffer[28]) << 24 | ((uint32_t)buffer[29]) << 16 | ((uint32_t)buffer[30]) << 8 | ((uint32_t)buffer[31]);

S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 8] = SWAP_UINT32(msg_tx.data.longs[6]);//((uint32_t)buffer[24]) << 24 | ((uint32_t)buffer[25]) << 16 | ((uint32_t)buffer[26]) << 8 | ((uint32_t)buffer[27]);

S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 7] = SWAP_UINT32(msg_tx.data.longs[5]);//((uint32_t)buffer[20]) << 24 | ((uint32_t)buffer[21]) << 16 | ((uint32_t)buffer[22]) << 8 | ((uint32_t)buffer[23]);

S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 6] = SWAP_UINT32(msg_tx.data.longs[4]);//((uint32_t)buffer[16]) << 24 | ((uint32_t)buffer[17]) << 16 | ((uint32_t)buffer[18]) << 8 | ((uint32_t)buffer[19]);

S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 5] = SWAP_UINT32(msg_tx.data.longs[3]);//((uint32_t)buffer[12]) << 24 | ((uint32_t)buffer[13]) << 16 | ((uint32_t)buffer[14]) << 8 | ((uint32_t)buffer[15]);

S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 4] = SWAP_UINT32(msg_tx.data.longs[2]);//((uint32_t)buffer[8]) << 24 | ((uint32_t)buffer[9]) << 16 | ((uint32_t)buffer[10]) << 8 | ((uint32_t)buffer[11]);

S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 3] = SWAP_UINT32(msg_tx.data.longs[1]);//((uint32_t)buffer[4]) << 24 | ((uint32_t)buffer[5]) << 16 | ((uint32_t)buffer[6]) << 8 | ((uint32_t)buffer[7]);

S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 2] = SWAP_UINT32(msg_tx.data.longs[0]);//((uint32_t)buffer[0]) << 24 | ((uint32_t)buffer[1]) << 16 | ((uint32_t)buffer[2]) << 8 | ((uint32_t)buffer[3]);

S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 1] = Can_ID; /* MB8 word 1: Tx msg with given ID */

TLE9261_Write(0x40, 0x5F);/*Monitor Point 2*/

S32K_CAN(Tx_handle).RAMn[CAN_USED_HRH_NUM*CAN_MSG_BUF_SIZE + 0] = CAN_RAMn_EDL(1) /* EDL=1 CAN FD format frame*/

|CAN_RAMn_BRS(1) /* BRS=1: Bit rate is switched inside msg */

|CAN_RAMn_ESI(0) /* ESI=0: ??? */

|CAN_RAMn_CODE(CAN_TX_MB_CODE_TRANS) /* CODE=0xC: Activate msg buf to transmit */

|CAN_RAMn_SRR(0) /* SRR=1 Tx frame (not req'd for std ID) */

|CAN_RAMn_IDE(0) /* IDE=0: Standard ID */

|CAN_RAMn_RTR(0) /* RTR = 0: data, not remote tx request frame*/

|CAN_RAMn_DLC(dlc); /* DLC=x; 1,2,3,4,5,6,7,8, 9-12,10-16, 11-20, 12-24, 13-32, 14-48, 15-64bytes */

TLE9261_Write(0x40, 0x5F);/*Monitor Point 3*/

// while (!(S32K_CAN(Tx_handle).IFLAG1 & 0x100)) {}; /* Wait for CAN 0 MB 8 flag */

// S32K_CAN(Tx_handle).IFLAG1 = 0x00000100; /* Clear CAN 0 MB 8 flag without clearing others*/

gs_CanControllerStatus[i] = CAN_STATUS_TRANSMITTING;

ret = BL_ERR_OK;

}

} while(0);

return ret;

}

The 1st monitor point is put before set ID for MB, 2nd monitor code is put just before update the code of MB to 0xC(transmit), 3rd monitor point is put just after update the code of MB to transmit.

I debug the code, and find the 2 phenomenons which I will describe as below:

1. Firstly I send a diag request service to read DID, test send 0x22 F1 87 on bus, but ECU not response. From the attached picture named 'Received request but no response' you can see ECU actually received the request message, and it is going to send the response and update the MB(monitor point 1 ,2 and 3 are captured in this snapshot), but no response message was monitored on CAN Tx PIN;

2. Then I monitor the ESR1, IFALG1 and RAM registor, and find that the code of transmit MB has been updated to 0xC(transmit) successfully, and the CAN bus is IDLE and no other error in ESR1 registor， But the message was not transmitted on CANTx, it seems flexCAN0 not ready to start to transmit which cause the message was stuck in SMB;

3. Thirdly I try to send another diag request, so I send 0x10 01 service, then ECU response rapidly with 0x62 F1 87.... you can see in the attached picture named 'New received request triggered the transmit of the reponse of last request.'. the message was transmitted before the code of monitor point 1, 2, 3, was executed. So It seems a newly request message trigger ECU to transmit the response of last request!!! which seems so unreasonable..

I really need your kind support to figure out this issue, thanks a lot.

Re: Re S32K146 Transmit Delay

PetrS — Tue, 16 Sep 2025 13:37:35 GMT

Hi,

it looks that for some reason after MB is written, the arbitration is not started or not finished and message is not moved-out to TX SMB. As the bus is idle, it should be performed normally.
Then if another message is received, new arbitration is started during CRC part, winner (out of single TX MB) selected and moved-out to SMB. Finally transmitted on first opportunity.
But also picture 'New received request triggered the transmit of the response of last request.' shows you actually update the TX MB before it is successfully transmitted. You should not get to Monitor point 1 if checking for MB transfer/availability is done properly.
Not sure what to suggest more. Check system and module clocking. Check the code to be sure TX is written when previous transfer was finished. Do you inactivation/abort of the MB in code?

BR, Petr

Re: Re S32K146 Transmit Delay

Kofi_Wang1 — Wed, 17 Sep 2025 10:29:17 GMT

Hello Petrs

I tried to adjust the MB sequence, it can transmit normally, But I still can't understand the deep logic why it is OK? Let me describe my method briefly:

I adjust the MB index used to receive or transmit, that is, originally MB0 is used to receive physical address diag message(ID:0x714), MB1 is used to receive functional address diag message(ID:0x7DF) , MB6 is used to transmit the ECU response message(ID:0x794).

The new one is: MB0 is used to transmit the ECU response message(ID:0x794), MB1 is used to receive physical address diag message(ID:0x714), MB2 is used to receive functional address diag message(ID:0x7DF).

After this adjustion, my ECU can receive or transmit normally. So I guess is it because MB6 fails to win the arbitration within flexCAN0, so ECU will not move the message to SMB? Since I only have 1 message to transmit, so it seems no other MB to arbitrate with MB6.

Also I will try to abort the MB if it is still transmitting when it need to start a new transmission.

Thanks alot.

Re: Re S32K146 Transmit Delay

PetrS — Fri, 19 Sep 2025 11:19:26 GMT

Hi,

I am not exactly able to explain the cause of this behavior without knowing the exact settings and code used. Seems the arbitration can be stopped or is pending for some reason, could be for example writing to any MB CS word before arbitration scans whole MBs.
The arbitration process scans the MBs, searching for the transmission MB that holds the message to be sent at the next opportunity. The scan starts from the lowest number MB and continues to the higher ones. If MB0 is used for transmission, upon writing to this MB, arbitration process starts and winner can be found immediately.

BR, Petr