topic Re: s32k LPSPI RX FIFO clearing and NO Stall option in S32K

s32k LPSPI RX FIFO clearing and NO Stall option

christianhdz — Wed, 05 Jun 2019 17:55:46 GMT

Hi,

I have some questions regarding the use of LPSPI:

I am using S32K144 micro to communicate through SPI as a Master.

I am observing that when the RxFIFO in LPSPI1_FSR-> RXCOUNT reaches the maximum (4), it makes the CS line to be held. I have the NO STALL option set to 0 for my LPSPI port, so I understand is actually STALLING the SPI.

If I debug, and have my debugger monitor the Register LPSPI1_FSR, when executing step by step, the RXCount is decremented on each step and alwas is either 1 or 0. However, when I use breakpoints to check why the SPI is not communicating I see that the register shows RXcount=4.

I am using only Transmit (TX) commands to write to another device through SPI. In most of the code I am using, I am not interested in reading the the info coming from the slave. i.e. I am triggering a watchdog trhough SPI, and I dont need to read the info in the RX line every time I trigger the watchdog.

Q: Does this mean that I need to flush the RX FIFO every time I do a TX? What is the most efficient way to do that?

Reading the LPSPI1_RDR->DATA register?

If I choose not to use the STALL option, by setting NO STALL=1, I still see the RX FIFO gets full and if I try to read, Q: the information it will not be from the last command I sent but from the first, right? do I need to purge the RX FIFO before trying to do a request to read from my slave device?

Re: s32k LPSPI RX FIFO clearing and NO Stall option

danielmartynek — Mon, 10 Jun 2019 11:24:35 GMT

Hi,

Have you considered using the Receive Data Mask TCR_RXMSK = 1 for such transfers?

Thanks,

BR, Daniel

Re: s32k LPSPI RX FIFO clearing and NO Stall option

christianhdz — Mon, 10 Jun 2019 18:01:13 GMT

Hi Daniel,

I tried it per your suggestion, however this disables the possibility of receiving any data right? Though most of my communication is through TX only, there are some cases where I need to "read" from the slave module some status.

What I I had tried before was to read the RDR register at least 4 times...

if ((LPSPI1->SR & LPSPI_SR_REF_MASK)||(LPSPI1->FSR!=0)){ /*Check if RX FIFO is empty, if not, CLEAR IT*/

SPI_data= LPSPI1->RDR;
SPI_data= LPSPI1->RDR;
SPI_data= LPSPI1->RDR;
SPI_data= LPSPI1->RDR;
SPI_data= LPSPI1->RDR;
}

But sometimes while debugging, before entering to a Write or Read SPI routine, I check the FIFO register and it still appears there is 1 object in the RXFIFO

Re: s32k LPSPI RX FIFO clearing and NO Stall option

danielmartynek — Thu, 13 Jun 2019 12:42:01 GMT

Hi Juan,

You can change the command with another write to the Transmit Command Register (TCR) whenever you need.

You can use two commands, one command for TX only and one for receiving the status data.

Please note that the TCR register should only be written using 32-bit writes.

Regards,

Daniel