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    <title>topic Re: S32K312 Understanding SRAM in S32K</title>
    <link>https://community.nxp.com/t5/S32K/S32K312-Understanding-SRAM/m-p/2154983#M51979</link>
    <description>Ohhokay understood.&lt;BR /&gt;Much thanks for the clarification</description>
    <pubDate>Wed, 20 Aug 2025 06:36:25 GMT</pubDate>
    <dc:creator>Hareesh_S</dc:creator>
    <dc:date>2025-08-20T06:36:25Z</dc:date>
    <item>
      <title>S32K312 Understanding SRAM</title>
      <link>https://community.nxp.com/t5/S32K/S32K312-Understanding-SRAM/m-p/2150068#M51746</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I am using an S32K312 MCU and have run out of SRAM (&amp;gt;32KB).&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Hareesh_S_0-1754913458015.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/351799i1AA33793410B42E3/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Hareesh_S_0-1754913458015.png" alt="Hareesh_S_0-1754913458015.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;From my understanding, the K312 has 96KB of SRAM, where 32KB is standby RAM, 32KB is no_cacheable and the last 32KB is shareable.&lt;/P&gt;&lt;P&gt;I do not fully understand the practical limitation to these sections, specifically with respect to the shareable section, given that the K312 is a single core and non-lockstep MCU. (I assume no_cacheable implies that data here cannot be moved to cache?)&lt;/P&gt;&lt;P&gt;Is there a section of the reference manual I should refer to for more information on this? All I have found is AN13388 but it only seems to describe the standby section in detail.&lt;/P&gt;&lt;P&gt;Additionally, what are&amp;nbsp;int_sram_fls_rsv, int_sram_results and&amp;nbsp;int_stack_dtcm sections for?&lt;/P&gt;&lt;P&gt;Tying back to my initial problem, if I am using more than 32KB ram (statically) do I need to manually place certain variables in the other ram sections? And how does this behaviour change WRT stack/heap? Can my stack/heap grow more than 32KB?&lt;/P&gt;&lt;P&gt;Much thanks in advance!&lt;/P&gt;</description>
      <pubDate>Mon, 11 Aug 2025 11:58:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K312-Understanding-SRAM/m-p/2150068#M51746</guid>
      <dc:creator>Hareesh_S</dc:creator>
      <dc:date>2025-08-11T11:58:34Z</dc:date>
    </item>
    <item>
      <title>Re: S32K312 Understanding SRAM</title>
      <link>https://community.nxp.com/t5/S32K/S32K312-Understanding-SRAM/m-p/2150929#M51792</link>
      <description>&lt;P&gt;&lt;BR /&gt;int_pflash: Main program flash memory for storing application code.&lt;BR /&gt;int_dflash: Non-volatile memory for storing persistent data like configuration or logs.&lt;BR /&gt;int_itcm: Fast memory for critical code execution with zero wait states.&lt;BR /&gt;int_dtcm: Fast memory for frequently accessed data with deterministic timing.&lt;BR /&gt;int_stack_dtcm: Dedicated fast memory for the stack to ensure reliable execution.&lt;BR /&gt;int_sram: General-purpose SRAM for variables, buffers, and heap.&lt;BR /&gt;int_sram_fls_rsv: Reserved SRAM for flash-related operations.&lt;BR /&gt;int_sram_no_cacheable: SRAM region excluded from caching, ideal for DMA or peripherals.&lt;BR /&gt;int_sram_results: Small reserved area for storing diagnostic or test results.&lt;BR /&gt;int_sram_shareable: Memory region intended for shared data, even in single-core use.&lt;BR /&gt;ram_rsvd2: Marker indicating the end of the SRAM address space.&lt;/P&gt;
&lt;P&gt;You can may change memory segment's addresses and sizes but it is needed to keep in mind boundaries given by memory resources.&lt;/P&gt;</description>
      <pubDate>Tue, 12 Aug 2025 12:44:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K312-Understanding-SRAM/m-p/2150929#M51792</guid>
      <dc:creator>davidtosenovjan</dc:creator>
      <dc:date>2025-08-12T12:44:26Z</dc:date>
    </item>
    <item>
      <title>Re: S32K312 Understanding SRAM</title>
      <link>https://community.nxp.com/t5/S32K/S32K312-Understanding-SRAM/m-p/2151470#M51817</link>
      <description>Hello,&lt;BR /&gt;Thank you for response.&lt;BR /&gt;So to clarify, am I right in saying there is no practical limitation on any of the SRAM segments and that I could theoretically group the whole 96KB into a single SRAM segment?</description>
      <pubDate>Wed, 13 Aug 2025 08:06:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K312-Understanding-SRAM/m-p/2151470#M51817</guid>
      <dc:creator>Hareesh_S</dc:creator>
      <dc:date>2025-08-13T08:06:34Z</dc:date>
    </item>
    <item>
      <title>Re: S32K312 Understanding SRAM</title>
      <link>https://community.nxp.com/t5/S32K/S32K312-Understanding-SRAM/m-p/2151485#M51820</link>
      <description>&lt;P&gt;I would recommend not to change used segments anyhow. You can use size of 0 in case it is not used anyhow.&lt;/P&gt;</description>
      <pubDate>Wed, 13 Aug 2025 08:22:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K312-Understanding-SRAM/m-p/2151485#M51820</guid>
      <dc:creator>davidtosenovjan</dc:creator>
      <dc:date>2025-08-13T08:22:33Z</dc:date>
    </item>
    <item>
      <title>Re: S32K312 Understanding SRAM</title>
      <link>https://community.nxp.com/t5/S32K/S32K312-Understanding-SRAM/m-p/2151782#M51829</link>
      <description>I do not intend on changing them, my question is merely to understand if there is a hard, physical limitation/difference between the different SRAM sections. Additionally, regarding the int_sram_shareable section, can you explain what "shared data" means in this case? Shared between what?&lt;BR /&gt;&lt;BR /&gt;Much thanks for the clarification thus far!</description>
      <pubDate>Wed, 13 Aug 2025 17:16:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K312-Understanding-SRAM/m-p/2151782#M51829</guid>
      <dc:creator>Hareesh_S</dc:creator>
      <dc:date>2025-08-13T17:16:43Z</dc:date>
    </item>
    <item>
      <title>Re: S32K312 Understanding SRAM</title>
      <link>https://community.nxp.com/t5/S32K/S32K312-Understanding-SRAM/m-p/2152276#M51843</link>
      <description>&lt;P&gt;It is rather generic for all S32K3 derivatives, so it is for sharing data between cores.&lt;/P&gt;
&lt;P&gt;Possibly it can be used it data are shared between core and other XBAR master as DMA or other. It could be certain AUTOSAR requirement - I am not completely sure.&lt;/P&gt;</description>
      <pubDate>Thu, 14 Aug 2025 09:36:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K312-Understanding-SRAM/m-p/2152276#M51843</guid>
      <dc:creator>davidtosenovjan</dc:creator>
      <dc:date>2025-08-14T09:36:03Z</dc:date>
    </item>
    <item>
      <title>Re: S32K312 Understanding SRAM</title>
      <link>https://community.nxp.com/t5/S32K/S32K312-Understanding-SRAM/m-p/2154983#M51979</link>
      <description>Ohhokay understood.&lt;BR /&gt;Much thanks for the clarification</description>
      <pubDate>Wed, 20 Aug 2025 06:36:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K312-Understanding-SRAM/m-p/2154983#M51979</guid>
      <dc:creator>Hareesh_S</dc:creator>
      <dc:date>2025-08-20T06:36:25Z</dc:date>
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