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    <title>S32KのトピックTechnical Inquiry Regarding Undefined Last Channel in ADC Instance</title>
    <link>https://community.nxp.com/t5/S32K/Technical-Inquiry-Regarding-Undefined-Last-Channel-in-ADC/m-p/2143174#M51453</link>
    <description>&lt;P&gt;Dear Technical Support Team,&lt;/P&gt;&lt;P&gt;I am writing to report an anomaly observed during ADC data acquisition debugging on an S32K312 microcontroller using the ​&lt;STRONG&gt;​Adc_TS_T40D34M20I2R0 MCAL package (SW32K3_RTD_4.4_2.0.2_D2211)​&lt;/STRONG&gt;​. The issue pertains to the incorrect definition of the ​&lt;STRONG&gt;​Last Channel​&lt;/STRONG&gt;​ in the ADC instance, specifically affecting DMA buffer population under specific configurations.&lt;/P&gt;&lt;H3&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;​&lt;STRONG&gt;​Issue Description​&lt;/STRONG&gt;​&lt;/H3&gt;&lt;OL&gt;&lt;LI&gt;&lt;P&gt;​&lt;STRONG&gt;​Configuration Context​&lt;/STRONG&gt;​:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;​&lt;STRONG&gt;​Trigger Mode​&lt;/STRONG&gt;​: Hardware-triggered conversion via Timer (1-second interval).&lt;/LI&gt;&lt;LI&gt;​&lt;STRONG&gt;​Data Transfer​&lt;/STRONG&gt;​: DMA-based data transport without interrupt (DMA interrupt handles data movement).&lt;/LI&gt;&lt;LI&gt;​&lt;STRONG&gt;​Channel Setup​&lt;/STRONG&gt;​: Configured multiple channels, with the last channel indexed as ​&lt;STRONG&gt;​Channel 72​&lt;/STRONG&gt;​ (as per EB28.2 configuration).&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dongxun_0-1753845747376.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/350116i487F889601646D24/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dongxun_0-1753845747376.png" alt="dongxun_0-1753845747376.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;​&lt;STRONG&gt;​Observed Behavior​&lt;/STRONG&gt;​:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;The first channel index in the configuration ​&lt;STRONG&gt;​fails to populate the designated DMA buffer​&lt;/STRONG&gt;​, despite the ​&lt;STRONG&gt;​PCDR register confirming successful data acquisition​&lt;/STRONG&gt;​ (register values match expected analog inputs).&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dongxun_1-1753845770693.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/350117iF99B07067D64BBEC/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dongxun_1-1753845770693.png" alt="dongxun_1-1753845770693.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/LI&gt;&lt;LI&gt;Debugging reveals that the function&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;Adc_Ipw_CalculateLastChan()&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;— responsible for determining the last converted channel — ​&lt;STRONG&gt;​consistently returns&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;AdcResultLastCh.AdcChnIdx = 0​&lt;/STRONG&gt;​ instead of the expected&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;72.&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dongxun_2-1753845819609.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/350118i53D2A6CD9AA81351/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dongxun_2-1753845819609.png" alt="dongxun_2-1753845819609.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;​&lt;STRONG&gt;​Root Cause Analysis​&lt;/STRONG&gt;​:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;In the function&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;Adc_Ipw_CalculateLastChan()&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;(invoked as&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;AdcResultLastCh = Adc_Ipw_CalculateLastChan(Group, ConversionType, CoreId);):&lt;UL&gt;&lt;LI&gt;The initialization of&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;AdcChnIdx&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;defaults to&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;0&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;and ​&lt;STRONG&gt;​never updates to reflect the configured last channel (Channel 72)​&lt;/STRONG&gt;​.&lt;/LI&gt;&lt;/UL&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;Subsequent logic (e.g., DMA buffer assignment) erroneously treats ​&lt;STRONG&gt;​Channel 0 as the last channel​&lt;/STRONG&gt;​, causing data for Channel 72 to be skipped in the buffer.&lt;/P&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dongxun_4-1753845869940.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/350120i556B1820845FD8DE/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dongxun_4-1753845869940.png" alt="dongxun_4-1753845869940.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dongxun_3-1753845852109.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/350119i454AB198FA8C2030/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dongxun_3-1753845852109.png" alt="dongxun_3-1753845852109.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;4. Code Modification​&lt;/STRONG&gt;​:&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P&gt;Revised&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;Adc_Ipw_CalculateLastChan()&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;to initialize&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;AdcChnIdx&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;with the ​&lt;STRONG&gt;​configured&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;LastCh&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;value (72)​&lt;/STRONG&gt;​ instead of&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;0.&lt;/P&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dongxun_5-1753848282647.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/350132iF57CB1A1A1BB8B5A/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dongxun_5-1753848282647.png" alt="dongxun_5-1753848282647.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;AdcChnIdx = ConfigPtr-&amp;gt;LastCh; &lt;SPAN class=""&gt;// Directly use configured last channel index &lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;​&lt;/SPAN&gt;&lt;STRONG&gt;​Validation Results​&lt;/STRONG&gt;&lt;SPAN&gt;​:&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;UL&gt;&lt;LI&gt;Post-modification,&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;AdcResultLastCh.AdcChnIdx&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;correctly returns ​&lt;STRONG&gt;​72​&lt;/STRONG&gt;​.&lt;/LI&gt;&lt;LI&gt;DMA buffer now ​&lt;STRONG&gt;​successfully captures data for all channels​&lt;/STRONG&gt;​, including Channel 72.&lt;/LI&gt;&lt;LI&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dongxun_6-1753848335987.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/350133iF081B060AB02410E/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dongxun_6-1753848335987.png" alt="dongxun_6-1753848335987.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;STRONG&gt;Open Questions​&lt;/STRONG&gt;&lt;SPAN&gt;​&lt;/SPAN&gt;&lt;OL&gt;&lt;LI&gt;&lt;P&gt;​&lt;STRONG&gt;​Potential Oversight​&lt;/STRONG&gt;​:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;Is there a configuration parameter or runtime condition (e.g., group/conversion mode) that&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;EM&gt;should&lt;/EM&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;update&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;AdcChnIdx&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;but was missed in our analysis?&lt;/LI&gt;&lt;LI&gt;Does the MCAL design implicitly assume Channel 0 as the last channel in certain modes?&lt;/LI&gt;&lt;/UL&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;​&lt;STRONG&gt;​Suspected Bug​&lt;/STRONG&gt;​:&lt;BR /&gt;Given that the default initialization (AdcChnIdx = 0) contradicts the configured channel topology, is this a ​&lt;STRONG&gt;​latent bug in the MCAL implementation​&lt;/STRONG&gt;​?&lt;/P&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;STRONG&gt;Request for Guidance​&lt;/STRONG&gt;&lt;SPAN&gt;​&lt;/SPAN&gt;&lt;UL&gt;&lt;LI&gt;Could you verify whether this behavior aligns with the intended design of&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;Adc_Ipw_CalculateLastChan()?&lt;/LI&gt;&lt;LI&gt;If confirmed as a bug, is there a planned patch for the MCAL package?&lt;/LI&gt;&lt;LI&gt;Alternatively, are there workarounds beyond the described fix?&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&amp;nbsp;Thank you for your expertise and prompt attention to this matter.&lt;/P&gt;Best reagrds,&lt;/LI&gt;&lt;/UL&gt;</description>
    <pubDate>Wed, 30 Jul 2025 04:17:45 GMT</pubDate>
    <dc:creator>dongxun</dc:creator>
    <dc:date>2025-07-30T04:17:45Z</dc:date>
    <item>
      <title>Technical Inquiry Regarding Undefined Last Channel in ADC Instance</title>
      <link>https://community.nxp.com/t5/S32K/Technical-Inquiry-Regarding-Undefined-Last-Channel-in-ADC/m-p/2143174#M51453</link>
      <description>&lt;P&gt;Dear Technical Support Team,&lt;/P&gt;&lt;P&gt;I am writing to report an anomaly observed during ADC data acquisition debugging on an S32K312 microcontroller using the ​&lt;STRONG&gt;​Adc_TS_T40D34M20I2R0 MCAL package (SW32K3_RTD_4.4_2.0.2_D2211)​&lt;/STRONG&gt;​. The issue pertains to the incorrect definition of the ​&lt;STRONG&gt;​Last Channel​&lt;/STRONG&gt;​ in the ADC instance, specifically affecting DMA buffer population under specific configurations.&lt;/P&gt;&lt;H3&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;​&lt;STRONG&gt;​Issue Description​&lt;/STRONG&gt;​&lt;/H3&gt;&lt;OL&gt;&lt;LI&gt;&lt;P&gt;​&lt;STRONG&gt;​Configuration Context​&lt;/STRONG&gt;​:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;​&lt;STRONG&gt;​Trigger Mode​&lt;/STRONG&gt;​: Hardware-triggered conversion via Timer (1-second interval).&lt;/LI&gt;&lt;LI&gt;​&lt;STRONG&gt;​Data Transfer​&lt;/STRONG&gt;​: DMA-based data transport without interrupt (DMA interrupt handles data movement).&lt;/LI&gt;&lt;LI&gt;​&lt;STRONG&gt;​Channel Setup​&lt;/STRONG&gt;​: Configured multiple channels, with the last channel indexed as ​&lt;STRONG&gt;​Channel 72​&lt;/STRONG&gt;​ (as per EB28.2 configuration).&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dongxun_0-1753845747376.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/350116i487F889601646D24/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dongxun_0-1753845747376.png" alt="dongxun_0-1753845747376.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;​&lt;STRONG&gt;​Observed Behavior​&lt;/STRONG&gt;​:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;The first channel index in the configuration ​&lt;STRONG&gt;​fails to populate the designated DMA buffer​&lt;/STRONG&gt;​, despite the ​&lt;STRONG&gt;​PCDR register confirming successful data acquisition​&lt;/STRONG&gt;​ (register values match expected analog inputs).&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dongxun_1-1753845770693.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/350117iF99B07067D64BBEC/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dongxun_1-1753845770693.png" alt="dongxun_1-1753845770693.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/LI&gt;&lt;LI&gt;Debugging reveals that the function&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;Adc_Ipw_CalculateLastChan()&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;— responsible for determining the last converted channel — ​&lt;STRONG&gt;​consistently returns&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;AdcResultLastCh.AdcChnIdx = 0​&lt;/STRONG&gt;​ instead of the expected&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;72.&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dongxun_2-1753845819609.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/350118i53D2A6CD9AA81351/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dongxun_2-1753845819609.png" alt="dongxun_2-1753845819609.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;​&lt;STRONG&gt;​Root Cause Analysis​&lt;/STRONG&gt;​:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;In the function&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;Adc_Ipw_CalculateLastChan()&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;(invoked as&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;AdcResultLastCh = Adc_Ipw_CalculateLastChan(Group, ConversionType, CoreId);):&lt;UL&gt;&lt;LI&gt;The initialization of&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;AdcChnIdx&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;defaults to&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;0&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;and ​&lt;STRONG&gt;​never updates to reflect the configured last channel (Channel 72)​&lt;/STRONG&gt;​.&lt;/LI&gt;&lt;/UL&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;Subsequent logic (e.g., DMA buffer assignment) erroneously treats ​&lt;STRONG&gt;​Channel 0 as the last channel​&lt;/STRONG&gt;​, causing data for Channel 72 to be skipped in the buffer.&lt;/P&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dongxun_4-1753845869940.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/350120i556B1820845FD8DE/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dongxun_4-1753845869940.png" alt="dongxun_4-1753845869940.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dongxun_3-1753845852109.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/350119i454AB198FA8C2030/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dongxun_3-1753845852109.png" alt="dongxun_3-1753845852109.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;4. Code Modification​&lt;/STRONG&gt;​:&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P&gt;Revised&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;Adc_Ipw_CalculateLastChan()&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;to initialize&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;AdcChnIdx&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;with the ​&lt;STRONG&gt;​configured&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;LastCh&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;value (72)​&lt;/STRONG&gt;​ instead of&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;0.&lt;/P&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dongxun_5-1753848282647.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/350132iF57CB1A1A1BB8B5A/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dongxun_5-1753848282647.png" alt="dongxun_5-1753848282647.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;AdcChnIdx = ConfigPtr-&amp;gt;LastCh; &lt;SPAN class=""&gt;// Directly use configured last channel index &lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;​&lt;/SPAN&gt;&lt;STRONG&gt;​Validation Results​&lt;/STRONG&gt;&lt;SPAN&gt;​:&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;UL&gt;&lt;LI&gt;Post-modification,&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;AdcResultLastCh.AdcChnIdx&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;correctly returns ​&lt;STRONG&gt;​72​&lt;/STRONG&gt;​.&lt;/LI&gt;&lt;LI&gt;DMA buffer now ​&lt;STRONG&gt;​successfully captures data for all channels​&lt;/STRONG&gt;​, including Channel 72.&lt;/LI&gt;&lt;LI&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dongxun_6-1753848335987.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/350133iF081B060AB02410E/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dongxun_6-1753848335987.png" alt="dongxun_6-1753848335987.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;STRONG&gt;Open Questions​&lt;/STRONG&gt;&lt;SPAN&gt;​&lt;/SPAN&gt;&lt;OL&gt;&lt;LI&gt;&lt;P&gt;​&lt;STRONG&gt;​Potential Oversight​&lt;/STRONG&gt;​:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;Is there a configuration parameter or runtime condition (e.g., group/conversion mode) that&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;EM&gt;should&lt;/EM&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;update&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;AdcChnIdx&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;but was missed in our analysis?&lt;/LI&gt;&lt;LI&gt;Does the MCAL design implicitly assume Channel 0 as the last channel in certain modes?&lt;/LI&gt;&lt;/UL&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;​&lt;STRONG&gt;​Suspected Bug​&lt;/STRONG&gt;​:&lt;BR /&gt;Given that the default initialization (AdcChnIdx = 0) contradicts the configured channel topology, is this a ​&lt;STRONG&gt;​latent bug in the MCAL implementation​&lt;/STRONG&gt;​?&lt;/P&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;STRONG&gt;Request for Guidance​&lt;/STRONG&gt;&lt;SPAN&gt;​&lt;/SPAN&gt;&lt;UL&gt;&lt;LI&gt;Could you verify whether this behavior aligns with the intended design of&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;Adc_Ipw_CalculateLastChan()?&lt;/LI&gt;&lt;LI&gt;If confirmed as a bug, is there a planned patch for the MCAL package?&lt;/LI&gt;&lt;LI&gt;Alternatively, are there workarounds beyond the described fix?&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&amp;nbsp;Thank you for your expertise and prompt attention to this matter.&lt;/P&gt;Best reagrds,&lt;/LI&gt;&lt;/UL&gt;</description>
      <pubDate>Wed, 30 Jul 2025 04:17:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Technical-Inquiry-Regarding-Undefined-Last-Channel-in-ADC/m-p/2143174#M51453</guid>
      <dc:creator>dongxun</dc:creator>
      <dc:date>2025-07-30T04:17:45Z</dc:date>
    </item>
    <item>
      <title>Re: Technical Inquiry Regarding Undefined Last Channel in ADC Instance</title>
      <link>https://community.nxp.com/t5/S32K/Technical-Inquiry-Regarding-Undefined-Last-Channel-in-ADC/m-p/2144029#M51494</link>
      <description>&lt;P&gt;&lt;A href="mailto:Hi@dongxun" target="_blank"&gt;Hi@dongxun&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;I've taken the time to check the latest RTD versions, and the following changes have been made in RTD 4.0.0 and later, such as RTD 5.0.X and RTD 6.0.x.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Senlent_0-1753928173205.png" style="width: 636px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/350348i01BDA2B09F1A1F40/image-dimensions/636x313?v=v2" width="636" height="313" role="button" title="Senlent_0-1753928173205.png" alt="Senlent_0-1753928173205.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;This is likely a known and fixed bug. I recommend that you stop using older versions of RTD.&lt;/P&gt;
&lt;P&gt;You may encounter new issues later, but these issues may have been fixed in newer versions,&lt;/P&gt;
&lt;P&gt;and we don't have the resources to help you reproduce issues with older versions.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 31 Jul 2025 02:20:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Technical-Inquiry-Regarding-Undefined-Last-Channel-in-ADC/m-p/2144029#M51494</guid>
      <dc:creator>Senlent</dc:creator>
      <dc:date>2025-07-31T02:20:56Z</dc:date>
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