Cortex M4F PendSV with FPU

LijieDu — Sun, 20 Jul 2025 12:34:26 GMT

xPortPendSVHandler:

ldr r3, =pxCurrentTCB
ldr r2, [r3] /* r2 = pxCurrentTCB. */
ldr r1, [r2] /* r1 = Location where the context should be saved. */

/*------------ Save Context. ----------- */
mrs r3, control
mrs r0, psp
isb

add r0, r0, #0x20 /* Move r0 to location where s0 is saved. */
tst lr, #0x10
ittt eq
vstmiaeq r1!, {s16-s31} /* Store s16-s31. */
vldmiaeq r0, {s0-s16} /* Copy hardware saved FP context into s0-s16. */
vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */
sub r0, r0, #0x20 /* Set r0 back to the location of hardware saved context. */

stmia r1!, {r3-r11, lr} /* Store CONTROL register, r4-r11 and LR. */
ldmia r0, {r4-r11} /* Copy hardware saved context into r4-r11. */
stmia r1!, {r0, r4-r11} /* Store original PSP (after hardware has saved context) and the hardware saved context. */
str r1, [r2] /* Save the location from where the context should be restored as the first member of TCB. */

/*---------- Select next task. --------- */
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
cpsid i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
#endif
msr basepri, r0
dsb
isb
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
cpsie i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
#endif
bl vTaskSwitchContext
mov r0, #0
msr basepri, r0

/*------------ Program MPU. ------------ */
ldr r3, =pxCurrentTCB
ldr r2, [r3] /* r2 = pxCurrentTCB. */
add r2, r2, #4 /* r2 = Second item in the TCB which is xMPUSettings. */

dmb /* Complete outstanding transfers before disabling MPU. */
ldr r0, =0xe000ed94 /* MPU_CTRL register. */
ldr r3, [r0] /* Read the value of MPU_CTRL. */
bic r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
str r3, [r0] /* Disable MPU. */

ldr r0, =0xe000ed9c /* Region Base Address register. */
ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */

#ifdef configTOTAL_MPU_REGIONS
#if ( configTOTAL_MPU_REGIONS == 16 )
ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */
ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
#endif /* configTOTAL_MPU_REGIONS == 16. */
#endif

ldr r0, =0xe000ed94 /* MPU_CTRL register. */
ldr r3, [r0] /* Read the value of MPU_CTRL. */
orr r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
str r3, [r0] /* Enable MPU. */
dsb /* Force memory writes before continuing. */

/*---------- Restore Context. ---------- */
ldr r3, =pxCurrentTCB
ldr r2, [r3] /* r2 = pxCurrentTCB. */
ldr r1, [r2] /* r1 = Location of saved context in TCB. */

ldmdb r1!, {r0, r4-r11} /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */
msr psp, r0
stmia r0!, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r1!, {r3-r11, lr} /* r3 contains CONTROL register. r4-r11 and LR restored. */
msr control, r3

tst lr, #0x10
ittt eq
vldmdbeq r1!, {s0-s16} /* s0-s16 contain hardware saved FP context. */
vstmiaeq r0!, {s0-s16} /* Copy hardware saved FP context on the task stack. */
vldmdbeq r1!, {s16-s31} /* Restore s16-s31. */

str r1, [r2] /* Save the location where the context should be saved next as the first member of TCB. */
bx lr

I don't understand why it is S0~S16?

S0~S15 and status reg are pushed into stack by hardware, why copy it again?

Hope get your direction and advice！

Re: Cortex M4F PendSV with FPU

davidtosenovjan — Mon, 21 Jul 2025 10:39:20 GMT

There seems to be an error in the code. Could you please indicate where this code is taken from?

Re: Cortex M4F PendSV with FPU

LijieDu — Mon, 21 Jul 2025 23:48:31 GMT

Hi davidtosenovjan

It comes from :FreeRTOS-Kernel/portable/IAR/ARM_CM4F_MPU at main · FreeRTOS/FreeRTOS-Kernel · GitHub

Hope to get your advice, thanks very much

Re: Cortex M4F PendSV with FPU

davidtosenovjan — Tue, 22 Jul 2025 10:45:52 GMT

The code in the FreeRTOS-Kernel/portable/IAR/ARM_CM4F_MPU directory is maintained by Amazon.com, Inc.

You can do so by opening an issue or a pull request on the GitHub repository. The FreeRTOS team actively monitors these channels.

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