<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>S32KのトピックRe: S32K3XX - DMA transfer block</title>
    <link>https://community.nxp.com/t5/S32K/S32K3XX-DMA-transfer-block/m-p/2115111#M49833</link>
    <description>Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/160001"&gt;@danielmartynek&lt;/a&gt;,&lt;BR /&gt;I'm working on the S32K344 platform using the LPSPI module in slave mode with DMA support. My use case is as follows:&lt;BR /&gt;&lt;BR /&gt;The LPSPI slave is expected to receive 40 bytes of data per transfer.&lt;BR /&gt;&lt;BR /&gt;This transfer occurs 5 times in succession, resulting in a total of 200 bytes.&lt;BR /&gt;&lt;BR /&gt;I want the DMA RX interrupt (ISR) to be triggered only after all 5 transfers are complete, i.e., after the full 200 bytes have been received.&lt;BR /&gt;&lt;BR /&gt;In the DMA Configuration, I have enabled:&lt;BR /&gt;&lt;BR /&gt;Global Configuration&lt;BR /&gt;Transfer Configuration&lt;BR /&gt;&lt;BR /&gt;My questions:&lt;BR /&gt;&lt;BR /&gt;How can I configure the DMA (using RTD) to accumulate these 5 transfers and trigger an interrupt only after receiving the total 200 bytes?&lt;BR /&gt;&lt;BR /&gt;If this is not possible, would I need to handle each 40-byte transfer individually in the DMA RX ISR and use a counter in software to detect when 5 transfers have completed? If so, how can this be implemented?&lt;BR /&gt;&lt;BR /&gt;Any guidance would be greatly appreciated.&lt;BR /&gt;&lt;BR /&gt;Thanks in advance!</description>
    <pubDate>Thu, 12 Jun 2025 07:22:04 GMT</pubDate>
    <dc:creator>DiaDev</dc:creator>
    <dc:date>2025-06-12T07:22:04Z</dc:date>
    <item>
      <title>S32K3XX - DMA transfer block</title>
      <link>https://community.nxp.com/t5/S32K/S32K3XX-DMA-transfer-block/m-p/2112405#M49683</link>
      <description>&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I'm working with the &lt;STRONG&gt;S32K344 MCU&lt;/STRONG&gt; and need to implement &lt;STRONG&gt;block-based data transfers via DMA&lt;/STRONG&gt; from peripherals like SPI. My goal is to &lt;STRONG&gt;queue multiple blocks of data for continuous streaming without data loss&lt;/STRONG&gt;, starting from the &lt;STRONG&gt;very first data block&lt;/STRONG&gt;.&lt;/P&gt;&lt;H3&gt;Requirements:&lt;/H3&gt;&lt;UL&gt;&lt;LI&gt;&lt;P&gt;Wait until &lt;STRONG&gt;20 data samples are collected&lt;/STRONG&gt;&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;Trigger &lt;STRONG&gt;DMA transfer&lt;/STRONG&gt; using the &lt;STRONG&gt;Tx watermark condition&lt;/STRONG&gt;&lt;/P&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;H3&gt;Questions:&lt;/H3&gt;&lt;P&gt;In my application, I want to &lt;STRONG&gt;wait until 20 data samples are available&lt;/STRONG&gt;, and only then trigger a &lt;STRONG&gt;DMA transfer&lt;/STRONG&gt; under the &lt;STRONG&gt;Tx watermark condition&lt;/STRONG&gt;.&lt;/P&gt;&lt;P&gt;Could you please advise on:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;&lt;P&gt;How to configure this properly in &lt;STRONG&gt;S32DS&lt;/STRONG&gt;?&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;Any recommended settings in &lt;STRONG&gt;DMA TCD&lt;/STRONG&gt;, SPI FIFO, or interrupt configuration?&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;Whether there are any examples or best practices for queuing multiple DMA transfers for seamless streaming?&lt;/P&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;Thanks in advance for your help!&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Sun, 08 Jun 2025 12:43:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3XX-DMA-transfer-block/m-p/2112405#M49683</guid>
      <dc:creator>DiaDev</dc:creator>
      <dc:date>2025-06-08T12:43:04Z</dc:date>
    </item>
    <item>
      <title>Re: S32K3XX - DMA transfer block</title>
      <link>https://community.nxp.com/t5/S32K/S32K3XX-DMA-transfer-block/m-p/2112612#M49697</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/248971"&gt;@DiaDev&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;This was already discussed in this thread:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/S32K/S32K3-DMA-Block-Based-Queuing-for-Continuous-Peripheral-Data/m-p/2112135#M49671" target="_blank" rel="noopener"&gt;https://community.nxp.com/t5/S32K/S32K3-DMA-Block-Based-Queuing-for-Continuous-Peripheral-Data/m-p/2112135#M49671&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;The LPSPI modules have just 4x32 bit RX FIFOs.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="danielmartynek_0-1749451966427.png" style="width: 648px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/341913iD1AB48BC68B72ED5/image-dimensions/648x190?v=v2" width="648" height="190" role="button" title="danielmartynek_0-1749451966427.png" alt="danielmartynek_0-1749451966427.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The DMA can be triggered by the LPSPI module when there are 4 words received.&lt;/P&gt;
&lt;P&gt;The RTD SPI drivers do not use the FIFO though.&lt;/P&gt;
&lt;P&gt;Anyway, there are these RTD examples for your reference:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-SPI-Transmit-amp-Receive-Using-Interrupt-DS3-5/ta-p/2011866" target="_blank" rel="noopener"&gt;https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-SPI-Transmit-amp-Receive-Using-Interrupt-DS3-5/ta-p/2011866&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-Continuous-SPI-Transmit-amp-Receive-Using-DMA/ta-p/2024597" target="_blank" rel="noopener"&gt;https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-Continuous-SPI-Transmit-amp-Receive-Using-DMA/ta-p/2024597&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR, Daniel&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 09 Jun 2025 07:37:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3XX-DMA-transfer-block/m-p/2112612#M49697</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2025-06-09T07:37:25Z</dc:date>
    </item>
    <item>
      <title>Re: S32K3XX - DMA transfer block</title>
      <link>https://community.nxp.com/t5/S32K/S32K3XX-DMA-transfer-block/m-p/2115111#M49833</link>
      <description>Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/160001"&gt;@danielmartynek&lt;/a&gt;,&lt;BR /&gt;I'm working on the S32K344 platform using the LPSPI module in slave mode with DMA support. My use case is as follows:&lt;BR /&gt;&lt;BR /&gt;The LPSPI slave is expected to receive 40 bytes of data per transfer.&lt;BR /&gt;&lt;BR /&gt;This transfer occurs 5 times in succession, resulting in a total of 200 bytes.&lt;BR /&gt;&lt;BR /&gt;I want the DMA RX interrupt (ISR) to be triggered only after all 5 transfers are complete, i.e., after the full 200 bytes have been received.&lt;BR /&gt;&lt;BR /&gt;In the DMA Configuration, I have enabled:&lt;BR /&gt;&lt;BR /&gt;Global Configuration&lt;BR /&gt;Transfer Configuration&lt;BR /&gt;&lt;BR /&gt;My questions:&lt;BR /&gt;&lt;BR /&gt;How can I configure the DMA (using RTD) to accumulate these 5 transfers and trigger an interrupt only after receiving the total 200 bytes?&lt;BR /&gt;&lt;BR /&gt;If this is not possible, would I need to handle each 40-byte transfer individually in the DMA RX ISR and use a counter in software to detect when 5 transfers have completed? If so, how can this be implemented?&lt;BR /&gt;&lt;BR /&gt;Any guidance would be greatly appreciated.&lt;BR /&gt;&lt;BR /&gt;Thanks in advance!</description>
      <pubDate>Thu, 12 Jun 2025 07:22:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3XX-DMA-transfer-block/m-p/2115111#M49833</guid>
      <dc:creator>DiaDev</dc:creator>
      <dc:date>2025-06-12T07:22:04Z</dc:date>
    </item>
    <item>
      <title>Re: S32K3XX - DMA transfer block</title>
      <link>https://community.nxp.com/t5/S32K/S32K3XX-DMA-transfer-block/m-p/2115129#M49836</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/248971"&gt;@DiaDev&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;This is not possible.&amp;nbsp;The DMA does not have any buffer.&lt;/P&gt;
&lt;P&gt;Although the LPSPI does have a buffer, it is just 4x32bit, and the RTD MCAL/IP SPI drivers do not use it.&lt;/P&gt;
&lt;P&gt;You don't need to configure the DMA if you use RTD.&lt;/P&gt;
&lt;P&gt;The SPI drivers configures the DMA -&amp;nbsp;Refer to the examples I linked here.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR, Daniel&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 12 Jun 2025 07:35:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3XX-DMA-transfer-block/m-p/2115129#M49836</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2025-06-12T07:35:25Z</dc:date>
    </item>
    <item>
      <title>Re: S32K3XX - DMA transfer block</title>
      <link>https://community.nxp.com/t5/S32K/S32K3XX-DMA-transfer-block/m-p/2115209#M49839</link>
      <description>Then can you share me link?</description>
      <pubDate>Thu, 12 Jun 2025 08:32:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3XX-DMA-transfer-block/m-p/2115209#M49839</guid>
      <dc:creator>DiaDev</dc:creator>
      <dc:date>2025-06-12T08:32:52Z</dc:date>
    </item>
    <item>
      <title>Re: S32K3XX - DMA transfer block</title>
      <link>https://community.nxp.com/t5/S32K/S32K3XX-DMA-transfer-block/m-p/2115971#M49868</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/248971"&gt;@DiaDev&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;There are two examples linked in this thread already by me.&lt;/P&gt;</description>
      <pubDate>Fri, 13 Jun 2025 08:17:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3XX-DMA-transfer-block/m-p/2115971#M49868</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2025-06-13T08:17:11Z</dc:date>
    </item>
  </channel>
</rss>

