topic Re: S32K344 Ethernet Not linking in S32K

S32K344 Ethernet Not linking

kual_gettobyte — Sat, 24 May 2025 14:48:45 GMT

I have made a custom S32K344 Board. Whose Schematic's is this one: S32K344 Evaluation Board (2).pdf

On Page 8: is the schematic diagram of Ethernet part using TJA1103 Ethernet Transceiver IC.

In software, i am using lwip_baremetal_S32k344 example provided by NXP.

But my code is stuck at particular this part:

kual_gettobyte_0-1748096545673.png

Though this code work's perfectly fine with the S32K3X4EVB-T172 Evaluation Board for Automotive General Purpose | NXP Semiconductors But, it doesnt seam to work with our hardware. Whose schematic have share above.

Can one suggest??? In our board, we have made the schematic's for ethernet section, exactly identical with Original S32K3X4-EVB 172.

Just changes of some Ethernet Pin's.

As according to code, it is waiting to establish the link. Does it because ethernet IC is not wake UP? Like do we have to configure TJA1103 with some pin's high/low. As in our custom hardware, we have made ethernet transceiver circuit exactly identical and same with original NXP S32K3x4 EVB Board.

Re: S32K344 Ethernet Not linking

PavelL — Mon, 26 May 2025 06:07:24 GMT

Hello @kual_gettobyte ,

please read & check register PHY_STATE 0x810C (mmd=30). That will guide you what TJA1103 needs.

Check also BIT 14 (master/slave settings) in and BASE_T1_PMA_CONTROL register 0x834 (mmd=1).

Best regards,

Pavel

Re: S32K344 Ethernet Not linking

kual_gettobyte — Mon, 26 May 2025 08:49:04 GMT

I read 0x810C Register, and it is returning 0 value for it.

kual_gettobyte_0-1748248058236.png

On working mode, reading this read's gives 3085. Which mean's that transmit state and basic state are active.

But in other board, reading 0x810C gives 0, means both transmit and basis state are disabled. So does it mean, that TJA1103 is not powered or it is fake one?? or some thing's needs to be done at hardware end??

And i found one thing to observer, the same software code is able to detect Phy TJA1103 IC, in the case of custom board at Phy addr 2. Whearas in Original Board it detect TJA1103 IC at Phy addr of 1.

kual_gettobyte_1-1748249269336.png

Can this mean something?? with respect to configurationally??

Re: S32K344 Ethernet Not linking

kual_gettobyte — Mon, 26 May 2025 09:04:42 GMT

Also one more observation i found.

As suggested of reading BASE_T1_PMA_Control Register of MMD 1

In Custom S32K3x4 Board, It return's with 0x8000. Which mean's TJA1103 is in Slave Mode.

I guess, that might be the reason??

How should i configure board in Master Board??

I saw a note, stating:

kual_gettobyte_0-1748250140518.png

So is it possible, that in custom board TJA1103 is in deep sleep mode?? If yes then how can i wake it up!?

In short:

1) I guess TJA1103 is configured in slave mode. So how to configure it in Master Mode?

2) I guess TJA1103 is in deep sleep mode, so how can i check that whether Phy is in deep sleep mode or awake?

These are my assumption's and understanding, let me know if their can be any other concerning way's.

Re: S32K344 Ethernet Not linking

PavelL — Mon, 26 May 2025 10:37:55 GMT

Hello @kual_gettobyte ,

Yes, master/slave has to be set properly for 100BASE-T1.

Master/slave can be easily changed by this code snippet example:

Gmac_Ip_MDIOWriteMMD(CFG_PHY_CTRL_IDX, phy_addr, 30U, 0x40U, 1U << 13, 1U); /* SUPER_CONFIG_ENABLE*/

Gmac_Ip_MDIOReadMMD(CFG_PHY_CTRL_IDX, phy_addr, 1U, 0x834U, &phy_reg_val0, 1U); /* BASE_T1_PMA_CONTROL */
Gmac_Ip_MDIOWriteMMD(CFG_PHY_CTRL_IDX, phy_addr, 1U, 0x834U, 1U << 14, 1U); /* set MASTER */
Gmac_Ip_MDIOReadMMD(CFG_PHY_CTRL_IDX, phy_addr, 1U, 0x834U, &phy_reg_val0, 1U);

Don't forget to clear SUPER_CONFIG_ENABLE once you are done with PHY settings.

It looks like you used different values for pin strap resistors: 4k7 vs. recommended 10k.

Your pin strap settings are the same as T172, so it's weird that you have different PHYAD (and other settings). Please double check RST_N signal and all supplies of the PHY.

Best regards,

Pavel

Re: S32K344 Ethernet Not linking

kual_gettobyte — Mon, 26 May 2025 14:34:08 GMT

Well i put your code.

Using that, Phy is set to Master Mode as on reading 0x834 register it now return's 0xC000. Which means TJA1103 Phy is in master mode.

kual_gettobyte_0-1748269889619.png

But Still, linking doesnt happen.

As on reading 0x810C: Phy State value it still give's 0x00. That is transmit and basic state are not active.

Could change of Phy address, as stated in my last comment. Can be any issue or point of major concern??

Any other register, you can state which i can check. Any register that tell's about sleep mode/wake mode of PHY after Master mode setting.

Else i will check signal's on pin strapping via multimeter and debug are their configuration's correct.

Re: S32K344 Ethernet Not linking

PavelL — Tue, 27 May 2025 06:36:05 GMT

Hello @kual_gettobyte ,

if two boards have the same HW pin strapping, they should also have the same reading of the pin strapping. Checking supply, reset and clocks should be the very first checks.

PHY_STATE definitely shall not be 0x00.

Please try to read ALWAYS_ACCESSIBLE register:

Gmac_Ip_MDIORead(CFG_PHY_CTRL_IDX, phy_addr, 0x1FU, &phy_reg_val1, 1U);

You may also read PMA_CONTROL1 register 0x00, mmd=1.

Best regards,

Pavel

Re: S32K344 Ethernet Not linking

kual_gettobyte — Tue, 27 May 2025 08:24:20 GMT

Hi, I did check all pin strapping configurations at hardware level.

All marked in yellow, are the one's which is they're in both boards. And the once in Red is difference.

kual_gettobyte_0-1748333221351.png

So Phy addr, coming out to be 2 now make's sense because in our board Config 2 is Pull down. Whereas in NXP Original Board it is Pull UP.

I check the reset signal's as well; it is Pull Up in both of the hardware.

But still on reading 0x810C register of MMD 30 it gives 0x00 value.

kual_gettobyte_0-1748333681384.png

kual_gettobyte_2-1748333783241.png

Meaning that PHY is not operational and it is disabled from transmit/basic state.

What can be possible, reasons for that, if software is exactly same and hardware configuration as well apart from just Phy addr and some Ethernet pin change's.!???

As I read on the datasheet, i found that PHY report's disabled if it is in PMA test mode or diagnostic state.

kual_gettobyte_3-1748333866318.png

How to check this and make Phy come out of diagnostic or test state!?

Will be expecting a quick reply, please!!!!

Re: S32K344 Ethernet Not linking

PavelL — Tue, 27 May 2025 08:38:43 GMT

Hello @kual_gettobyte ,

Please try to read ALWAYS_ACCESSIBLE register:

Gmac_Ip_MDIORead(CFG_PHY_CTRL_IDX, phy_addr, 0x1FU, &phy_reg_val1, 1U);

You may also read PMA_CONTROL1 register 0x00, mmd=1.

Have you checked supplies, clock and RST_N?

Best regards,

Pavel

Re: S32K344 Ethernet Not linking

kual_gettobyte — Tue, 27 May 2025 09:11:14 GMT

Reading ALWAYS_ACCESSIBLE register, give's value of : 0x27

and reading PMA_CONTROL1, give's reset value of: 0x2000

On reading this bit's and register description. What i can assume, PHY is powered correctly and not in sleep mode. As first 3 bits of ALWAYS_ACCESSIBLE register, indicate whether Phy is getting correct power and it is not in sleep mode. But Phy register's are not writable. I didn't get, is it some INT pin configuration related of Phy

kual_gettobyte_0-1748336434964.png

And on reading PMA_CONTROL register's it return's reset value of 0x2000. And i guess something is wierd or wrong in this as speed select is selected of 10Mbit according to this register read. But it is written 10Mbit's is not supported.

kual_gettobyte_0-1748337019552.png

Any comment's on these??

I did check Reset and supplie's Phy is properly getting voltage of 3.3. And Clock signal's how should i check?? via probing to oscilliscope??

I guess Clock signal also must be working correct, as i am able to read and write Phy register's properly!?

Re: S32K344 Ethernet Not linking

kual_gettobyte — Tue, 27 May 2025 12:24:55 GMT

Well Accessible Register returning value of 0x27 mean's, its Bit 4 is 0, which mean's FUSA test has failed!!!

I dig the datasheet and also read the 0x42 register of MMD 30. Which tell's whether FUSA test has passed or failed. And i found that in our custom board FUSA test status bit are 0 meaning it is failing.

What can be rea Gmac_Ip_MDIOReadMMD(CFG_PHY_CTRL_IDX, phy_addr, 30, 0x313, &phy_reg_val3, 1U);
Gmac_Ip_MDIOReadMMD(CFG_PHY_CTRL_IDX, phy_addr, 30, 0x42, &phy_reg_val3, 1U);
Gmac_Ip_MDIOReadMMD(CFG_PHY_CTRL_IDX, phy_addr, 30, 0x31a, &phy_reg_val3, 1U);
Gmac_Ip_MDIOReadMMD(CFG_PHY_CTRL_IDX, phy_addr, 30, 0x319, &phy_reg_val3, 1U);
Gmac_Ip_MDIOReadMMD(CFG_PHY_CTRL_IDX, phy_addr, 30, 0x318, &phy_reg_val3, 1U);

But all of them shows that all voltages are fine.
son's for FUSA test failure??

As further i read following register's of MMD30:

Re: S32K344 Ethernet Not linking

PavelL — Tue, 27 May 2025 13:04:08 GMT

Hello @kual_gettobyte ,

let's focus on ALWAYS_ACCESSIBLE register first. The value 0x27 means:

bit 5 means that there is issue with a clock - OSC_WARN. Looking to your schematic, you use different xtal (compare to T172 board). Please check values of CX1 and CX2 - 27pF sounds high to me. Please check AN13137 TJA1103 Application note rev 2.0, chapter 3.9.2. where CX1, CX2 settings is discussed.
bit 2 : core supply is OK
bit 1 : device is not in sleep with INH deasserted, all registers are readable
bit 0: pin INH is driven high, i.e driven to VDDA_AO

Yes, please check clock signal by oscilloscope.

If clock is wrong, the FUSA failed too.

Best regards,

Pavel

Re: S32K344 Ethernet Not linking

kual_gettobyte — Tue, 27 May 2025 13:50:08 GMT

AN13137 is that secure doc?? i cant see on NXP website!

Re: S32K344 Ethernet Not linking

PavelL — Tue, 27 May 2025 14:02:59 GMT

Hello @kual_gettobyte ,

yes, it is secure file:

PavelL_0-1748354445693.png

Best regards,

Pavel