<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic S32K3 - PIT Clock in S32K</title>
    <link>https://community.nxp.com/t5/S32K/S32K3-PIT-Clock/m-p/2094246#M48596</link>
    <description>&lt;P&gt;Hello.&lt;/P&gt;&lt;P&gt;I am testing the Iseled example code.&lt;BR /&gt;PIT_0 and PIT_1 are connected to AIPS_SLOW and run at a 30 MHz clock.&lt;BR /&gt;Why is the GptChannelTickFrequency from the GPT module outputting as 60 MHz?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ssean_0-1746768846965.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/336826iD62C86B1C4D7DD09/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ssean_0-1746768846965.png" alt="ssean_0-1746768846965.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ssean_1-1746768857304.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/336827i772B7FB4C630F054/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ssean_1-1746768857304.png" alt="ssean_1-1746768857304.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ssean_2-1746768864041.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/336828iFAA7842E7A9FFB71/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ssean_2-1746768864041.png" alt="ssean_2-1746768864041.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;BRs,&lt;/P&gt;&lt;P&gt;Sean Sung&lt;/P&gt;</description>
    <pubDate>Fri, 09 May 2025 05:35:22 GMT</pubDate>
    <dc:creator>ssean</dc:creator>
    <dc:date>2025-05-09T05:35:22Z</dc:date>
    <item>
      <title>S32K3 - PIT Clock</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-PIT-Clock/m-p/2094246#M48596</link>
      <description>&lt;P&gt;Hello.&lt;/P&gt;&lt;P&gt;I am testing the Iseled example code.&lt;BR /&gt;PIT_0 and PIT_1 are connected to AIPS_SLOW and run at a 30 MHz clock.&lt;BR /&gt;Why is the GptChannelTickFrequency from the GPT module outputting as 60 MHz?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ssean_0-1746768846965.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/336826iD62C86B1C4D7DD09/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ssean_0-1746768846965.png" alt="ssean_0-1746768846965.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ssean_1-1746768857304.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/336827i772B7FB4C630F054/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ssean_1-1746768857304.png" alt="ssean_1-1746768857304.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ssean_2-1746768864041.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/336828iFAA7842E7A9FFB71/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ssean_2-1746768864041.png" alt="ssean_2-1746768864041.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;BRs,&lt;/P&gt;&lt;P&gt;Sean Sung&lt;/P&gt;</description>
      <pubDate>Fri, 09 May 2025 05:35:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-PIT-Clock/m-p/2094246#M48596</guid>
      <dc:creator>ssean</dc:creator>
      <dc:date>2025-05-09T05:35:22Z</dc:date>
    </item>
    <item>
      <title>Re: S32K3 - PIT Clock</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-PIT-Clock/m-p/2094389#M48605</link>
      <description>&lt;P&gt;Hello &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/215656"&gt;@ssean&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;The ClockReferencePoint is configured in the MCU driver: &lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="danielmartynek_0-1746775376540.png" style="width: 505px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/336869iB8CE34F8CBDC3FF0/image-dimensions/505x312?v=v2" width="505" height="312" role="button" title="danielmartynek_0-1746775376540.png" alt="danielmartynek_0-1746775376540.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="danielmartynek_1-1746775453582.png" style="width: 503px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/336870i49248202D07D0E01/image-dimensions/503x234?v=v2" width="503" height="234" role="button" title="danielmartynek_1-1746775453582.png" alt="danielmartynek_1-1746775453582.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;By the way, there is no clock option with CORE_CLK = 60MHz (RM, Section 24.7.2 System clocking configurations).&lt;/P&gt;
&lt;P&gt;We recommend using one of the clock options.&lt;/P&gt;
&lt;P&gt;At least the ratios between the clocks must be set to one of the clock options.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="danielmartynek_2-1746775659713.png" style="width: 514px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/336875iF19900DEE80A08D1/image-dimensions/514x152?v=v2" width="514" height="152" role="button" title="danielmartynek_2-1746775659713.png" alt="danielmartynek_2-1746775659713.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Daniel&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 09 May 2025 07:29:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-PIT-Clock/m-p/2094389#M48605</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2025-05-09T07:29:32Z</dc:date>
    </item>
    <item>
      <title>Re: S32K3 - PIT Clock</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-PIT-Clock/m-p/2094937#M48629</link>
      <description>&lt;P&gt;Dear&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/160001"&gt;@danielmartynek&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;There is no reference point for AIPS_SLOW_CLK in ISELED example project.&lt;/P&gt;&lt;P&gt;So I added like below.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ssean_0-1747004887290.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/337006iB2A4F530F03072A7/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ssean_0-1747004887290.png" alt="ssean_0-1747004887290.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The GptChannelTickFrequency of the GPT module is still outputting 60 MHz.&lt;BR /&gt;Shouldn't the GptChannelTickFrequency of the GPT and PIT modules be based on the AIPS_SLOW clock?&lt;BR /&gt;What configuration determines this output frequency?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have already reviewed the use of the 60 MHz Core Clock.&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/t5/S32K/S32K312-Core-Clock/td-p/1978738" target="_blank" rel="noopener"&gt;https://community.nxp.com/t5/S32K/S32K312-Core-Clock/td-p/1978738&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Is there any invalid setting value in my configuration?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;BRs,&lt;/P&gt;&lt;P&gt;Sean Sung.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sun, 11 May 2025 23:17:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-PIT-Clock/m-p/2094937#M48629</guid>
      <dc:creator>ssean</dc:creator>
      <dc:date>2025-05-11T23:17:49Z</dc:date>
    </item>
    <item>
      <title>Re: S32K3 - PIT Clock</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-PIT-Clock/m-p/2095286#M48647</link>
      <description>&lt;P&gt;Hello&amp;nbsp;Sean,&lt;/P&gt;
&lt;P&gt;The ratios between the clocks seems to match this option: RM, Table 161. Option F - Operation in 1:1 mode with CORE_CLK and AIPS_PLAT_CLK at same speed. &lt;/P&gt;
&lt;P&gt;However, can you use CLKOUT_RUN to confirm it?&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="danielmartynek_0-1747036771647.png" style="width: 522px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/337145i0D4F3FC1771E5976/image-dimensions/522x244?v=v2" width="522" height="244" role="button" title="danielmartynek_0-1747036771647.png" alt="danielmartynek_0-1747036771647.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Daniel&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 12 May 2025 08:00:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-PIT-Clock/m-p/2095286#M48647</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2025-05-12T08:00:24Z</dc:date>
    </item>
    <item>
      <title>Re: S32K3 - PIT Clock</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-PIT-Clock/m-p/2095789#M48674</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/160001"&gt;@danielmartynek&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Is this setting related to the Gpt module's GptChannelTickFrequency output?&lt;BR /&gt;Could you check the GptChannelTickFrequency first?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Clock setting is below.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ssean_0-1747091962121.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/337281iE047929C5212A738/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ssean_0-1747091962121.png" alt="ssean_0-1747091962121.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ssean_1-1747091979468.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/337282iF74F18CCBAF038DC/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ssean_1-1747091979468.png" alt="ssean_1-1747091979468.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;BRs,&lt;/P&gt;&lt;P&gt;Sean Sung&lt;/P&gt;</description>
      <pubDate>Mon, 12 May 2025 23:20:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-PIT-Clock/m-p/2095789#M48674</guid>
      <dc:creator>ssean</dc:creator>
      <dc:date>2025-05-12T23:20:45Z</dc:date>
    </item>
    <item>
      <title>Re: S32K3 - PIT Clock</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-PIT-Clock/m-p/2096207#M48699</link>
      <description>&lt;P&gt;Hello Sean,&lt;/P&gt;
&lt;P&gt;You need to use McuClockReferencePoint_1&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="danielmartynek_0-1747120328277.png" style="width: 703px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/337473i57AAC435DBD9E141/image-dimensions/703x143?v=v2" width="703" height="143" role="button" title="danielmartynek_0-1747120328277.png" alt="danielmartynek_0-1747120328277.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;How is GptClokcReferencePoint_0 configured in GptDriverConfiguration?&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="danielmartynek_1-1747120394800.png" style="width: 589px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/337475iC954EEE6C6739E22/image-dimensions/589x309?v=v2" width="589" height="309" role="button" title="danielmartynek_1-1747120394800.png" alt="danielmartynek_1-1747120394800.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 13 May 2025 07:14:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-PIT-Clock/m-p/2096207#M48699</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2025-05-13T07:14:28Z</dc:date>
    </item>
    <item>
      <title>Re: S32K3 - PIT Clock</title>
      <link>https://community.nxp.com/t5/S32K/S32K3-PIT-Clock/m-p/2096214#M48700</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/160001"&gt;@danielmartynek&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I made mistake that.&lt;/P&gt;&lt;P&gt;I was able to solve it using the method you suggested.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;BRs,&lt;/P&gt;&lt;P&gt;Sean Sung&lt;/P&gt;</description>
      <pubDate>Tue, 13 May 2025 07:18:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K3-PIT-Clock/m-p/2096214#M48700</guid>
      <dc:creator>ssean</dc:creator>
      <dc:date>2025-05-13T07:18:26Z</dc:date>
    </item>
  </channel>
</rss>

