topic S32K uC DMA setup time setting in S32K

S32K uC DMA setup time setting

OTSL-J — Mon, 05 May 2025 22:58:52 GMT

Please let us know if there is any setting that can reduce the DMA start processing time for SPI port DMA setup time.

*Background
We have confirmed a problem that SPI Read processing from the microcontroller cannot keep up with receiving frames from the network side and causes Receive overflow when using a multi-drop connection (bus type, multiple node connection) with 10BASE-T1S.

When verified with S32k3xx, it is confirmed that the DMA setup time of the SPI port is long, which may be interfering with the effective rate of the SPI port.
It takes about 24us from calling the function call LPSPI_LP_AsyncTransmit in the SDK until the CS signal on the SPI port actually goes Low.
We believe that if we can reduce the SPI DMA start processing time in the SDK, the throughput of the SPI port will be improved.

Re: S32K uC DMA setup time setting

PetrS — Tue, 06 May 2025 07:57:56 GMT

Hi,

there is no much options to do, I think, seems the drive adds some SW overhead.
You can consider below...
- configure DMA repeated transfer, check chapter 3.6.10 of the driver UM
- do not use LPSPIV2_E050456_2ND_SOLUTION, which adds some timeout at transfer start, see chapter 3.6.8 of the same UM.

BR, Petr

Re: S32K uC DMA setup time setting

OTSL-J — Tue, 06 May 2025 23:40:10 GMT

Where can I find documentation for driver UM?

Re: S32K uC DMA setup time setting

OTSL-J — Tue, 13 May 2025 04:15:30 GMT

>When verified with S32k3xx, it is confirmed that the DMA setup time of the SPI port is long, which may be interfering with the effective rate of the SPI port.

You contacted us by email, but it was a mistake for S32k1XX.
We could not find the correction in the attached screen in our environment.

Re: S32K uC DMA setup time setting

PetrS — Tue, 13 May 2025 07:56:02 GMT

Hi,

so you do not have S32K3, but S32K1xx and use SDK PAL driver. Am I right? What S32DS/SDK version do you have? Maybe you can try PD driver directly, not PAL one.
Anyway, as driver manages DMA itself, I do not expect its SW overhead can be reduced.

BR, Petr