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    <title>S32KのトピックRe: S32K144 PIT issue</title>
    <link>https://community.nxp.com/t5/S32K/S32K144-PIT-issue/m-p/2086266#M48098</link>
    <description>&lt;P&gt;Hi@&lt;SPAN&gt;vignesh3&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Please refer to the attachment.&lt;/P&gt;
&lt;P&gt;The hardware used is S32K144EVB and the IDE version is S32 Design Studio For Arm V2.2.&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;In fact, I couldn't compile your project from the beginning, and your code directly operated the registers without any instructions. I don't have time to help you check each register one by one, so I made a demo for your reference.&lt;/P&gt;</description>
    <pubDate>Thu, 24 Apr 2025 06:19:59 GMT</pubDate>
    <dc:creator>Senlent</dc:creator>
    <dc:date>2025-04-24T06:19:59Z</dc:date>
    <item>
      <title>S32K144 PIT issue</title>
      <link>https://community.nxp.com/t5/S32K/S32K144-PIT-issue/m-p/2074570#M47498</link>
      <description>&lt;DIV&gt;void clock_pll_init(void)&lt;/DIV&gt;&lt;DIV&gt;{&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;//select SOSC as input clock to the Micro controller&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;SCG-&amp;gt;SOSCCFG |= (1 &amp;lt;&amp;lt; 2);// need to check this bit&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;//select the pll source as SOSC&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;SCG-&amp;gt;SPLLCFG |= (1 &amp;lt;&amp;lt; 0);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;//set PREDIV to zero no need to devide the pll input clk&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;SCG-&amp;gt;SPLLCFG |= (0 &amp;lt;&amp;lt; 8);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;//multiply the input 8 Mhz by 45 to make clock as 360 Mhz&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;SCG-&amp;gt;SPLLCFG |= (29 &amp;lt;&amp;lt; 16);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;//bydefault the PLL output clock is devided by 2&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;//select SPLL_CLK as system clock in run mode&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;SCG-&amp;gt;RCCR |= (6 &amp;lt;&amp;lt; 24);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;//set the division factor for core clock and system clock core_clk = pllclock/1 = 180Mhz /1 - 180 Mhz&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;SCG-&amp;gt;RCCR |= (0 &amp;lt;&amp;lt; 16);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;//bus_clk = core_clk / 2 = 180 Mhz / 2 = 90 Mhz&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;SCG-&amp;gt;RCCR |= (1 &amp;lt;&amp;lt; 4);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;//flash_clk = core_clk / 6 = 180Mhz / 6 = 30Mhz&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;SCG-&amp;gt;RCCR |= (5 &amp;lt;&amp;lt; 0);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;//SPLLDIV1_CLK = PLL_CLK / 2 = 180Mhz / 2 = 90Mhz&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;SCG-&amp;gt;SPLLDIV |= (2 &amp;lt;&amp;lt; 0);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;//SPLLDIV2_CLK = PLL_CLK / 4 = 180Mhz / 4 = 45Mhz&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;SCG-&amp;gt;SPLLDIV |= (3 &amp;lt;&amp;lt; 8);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;//note:SPLLDIV1_CLK,SPLLDIV2_CLK these two clk can be used for any peripheral&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;void gpioInit(void)&lt;/DIV&gt;&lt;DIV&gt;{&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;//enable clock for PORTD&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;PCC-&amp;gt;PCCn[PCC_PORTD_INDEX] |= (1 &amp;lt;&amp;lt; 30);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;//select the PD0 as output pin&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;PTD-&amp;gt;PDDR |= (1 &amp;lt;&amp;lt; 0);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;//select PD0 as GPIO from mux&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;PORTD-&amp;gt;PCR[0] |= (1 &amp;lt;&amp;lt; 8);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;void pitChannelInit(void)&lt;/DIV&gt;&lt;DIV&gt;{&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;//select SPLLDIV2_CLK for LPIT peripheral&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;PCC-&amp;gt;PCCn[PCC_LPIT_INDEX] |= (6 &amp;lt;&amp;lt; 24);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;//enable clock for LPIT&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;PCC-&amp;gt;PCCn[PCC_LPIT_INDEX] |= (1 &amp;lt;&amp;lt; 30);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;//enable clock for LPIT0 module&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;LPIT0-&amp;gt;MCR = 1;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;//enable channel0 interrupt&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;LPIT0-&amp;gt;MIER = 1;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;//load time period value to the timer value register&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;LPIT0-&amp;gt;TMR[0].TVAL = 45000000;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;//enable the timer channel 0&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;LPIT0-&amp;gt;TMR[0].TCTRL |= (1 &amp;lt;&amp;lt; 0);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;when I am executing&amp;nbsp;&lt;SPAN&gt;LPIT0-&amp;gt;TMR[0].TVAL = 45000000; it is showing "Break at address "0xdeadbeee" with no debug information available, or outside of program code."&amp;nbsp;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;Can anyone tell me why I can not able to execute this line and what is the meaning of that note.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sat, 05 Apr 2025 11:32:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K144-PIT-issue/m-p/2074570#M47498</guid>
      <dc:creator>vignesh3</dc:creator>
      <dc:date>2025-04-05T11:32:04Z</dc:date>
    </item>
    <item>
      <title>Re: S32K144 PIT issue</title>
      <link>https://community.nxp.com/t5/S32K/S32K144-PIT-issue/m-p/2074953#M47524</link>
      <description>&lt;P&gt;Hi2&lt;SPAN&gt;vignesh3&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;This looks more like a debugger problem.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;I took a quick look at your code and it seems like there is nothing wrong with it.&lt;/P&gt;
&lt;P&gt;If you can reproduce the problem consistently, maybe you could tell me what debugger and&lt;/P&gt;
&lt;P&gt;hardware you are using and provide your project.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 07 Apr 2025 08:16:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K144-PIT-issue/m-p/2074953#M47524</guid>
      <dc:creator>Senlent</dc:creator>
      <dc:date>2025-04-07T08:16:58Z</dc:date>
    </item>
    <item>
      <title>Re: S32K144 PIT issue</title>
      <link>https://community.nxp.com/t5/S32K/S32K144-PIT-issue/m-p/2079732#M47729</link>
      <description>Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/188029"&gt;@Senlent&lt;/a&gt; I am using segger debugger with s32k144 development board still I am getting this issue can check it from your side.</description>
      <pubDate>Mon, 14 Apr 2025 07:59:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K144-PIT-issue/m-p/2079732#M47729</guid>
      <dc:creator>vignesh3</dc:creator>
      <dc:date>2025-04-14T07:59:24Z</dc:date>
    </item>
    <item>
      <title>Re: S32K144 PIT issue</title>
      <link>https://community.nxp.com/t5/S32K/S32K144-PIT-issue/m-p/2079735#M47730</link>
      <description>&lt;P&gt;Hi@&lt;SPAN&gt;vignesh3&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;yes,sure, please share your whole project , so that i can help you to check it on my side.&lt;/P&gt;</description>
      <pubDate>Mon, 14 Apr 2025 08:01:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K144-PIT-issue/m-p/2079735#M47730</guid>
      <dc:creator>Senlent</dc:creator>
      <dc:date>2025-04-14T08:01:30Z</dc:date>
    </item>
    <item>
      <title>Re: S32K144 PIT issue</title>
      <link>https://community.nxp.com/t5/S32K/S32K144-PIT-issue/m-p/2079743#M47731</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/188029"&gt;@Senlent&lt;/a&gt;&amp;nbsp;take quick check from your side.&lt;/P&gt;</description>
      <pubDate>Mon, 14 Apr 2025 08:09:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K144-PIT-issue/m-p/2079743#M47731</guid>
      <dc:creator>vignesh3</dc:creator>
      <dc:date>2025-04-14T08:09:30Z</dc:date>
    </item>
    <item>
      <title>Re: S32K144 PIT issue</title>
      <link>https://community.nxp.com/t5/S32K/S32K144-PIT-issue/m-p/2079803#M47735</link>
      <description>&lt;P&gt;Hi@&lt;SPAN&gt;vignesh3&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Your Lpit Module settings is no problem, but your clock setting is not right-&amp;gt;clock_pll_init,&lt;/P&gt;
&lt;P&gt;These clocks have exceeded the allowed threshold in run mode.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Senlent_0-1744622428813.png" style="width: 651px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/332871i4A45D8B7A19B3266/image-dimensions/651x173?v=v2" width="651" height="173" role="button" title="Senlent_0-1744622428813.png" alt="Senlent_0-1744622428813.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 14 Apr 2025 09:21:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K144-PIT-issue/m-p/2079803#M47735</guid>
      <dc:creator>Senlent</dc:creator>
      <dc:date>2025-04-14T09:21:09Z</dc:date>
    </item>
    <item>
      <title>Re: S32K144 PIT issue</title>
      <link>https://community.nxp.com/t5/S32K/S32K144-PIT-issue/m-p/2080042#M47748</link>
      <description>Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/188029"&gt;@Senlent&lt;/a&gt;,&lt;BR /&gt;I have checked in the RM but I could not able to find out clock threshold details.&lt;BR /&gt;Can you tell me where can I find these details in RM.</description>
      <pubDate>Mon, 14 Apr 2025 14:18:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K144-PIT-issue/m-p/2080042#M47748</guid>
      <dc:creator>vignesh3</dc:creator>
      <dc:date>2025-04-14T14:18:48Z</dc:date>
    </item>
    <item>
      <title>Re: S32K144 PIT issue</title>
      <link>https://community.nxp.com/t5/S32K/S32K144-PIT-issue/m-p/2080308#M47756</link>
      <description>&lt;P&gt;&lt;A href="mailto:Hi@vignesh3" target="_blank"&gt;Hi@vignesh3&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Please take a look at&lt;STRONG&gt; the chapter :"&lt;U&gt;27.4 Internal clocking requirements&lt;/U&gt;"&lt;/STRONG&gt; and&amp;nbsp;we have application note &lt;STRONG&gt;AN5408&lt;/STRONG&gt; to give you a better understanding of this.&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/docs/en/application-note/AN5408.pdf" target="_blank"&gt;https://www.nxp.com/docs/en/application-note/AN5408.pdf&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Aslo,we provided similar demo in S32 Design Studio for Arm V2.2, bare-metal demo code related to LPIT.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 15 Apr 2025 01:59:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K144-PIT-issue/m-p/2080308#M47756</guid>
      <dc:creator>Senlent</dc:creator>
      <dc:date>2025-04-15T01:59:24Z</dc:date>
    </item>
    <item>
      <title>Re: S32K144 PIT issue</title>
      <link>https://community.nxp.com/t5/S32K/S32K144-PIT-issue/m-p/2085490#M48067</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/188029"&gt;@Senlent&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Still I am having the same issue can you try from your side, I am attaching the modified code here below.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 23 Apr 2025 13:41:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K144-PIT-issue/m-p/2085490#M48067</guid>
      <dc:creator>vignesh3</dc:creator>
      <dc:date>2025-04-23T13:41:02Z</dc:date>
    </item>
    <item>
      <title>Re: S32K144 PIT issue</title>
      <link>https://community.nxp.com/t5/S32K/S32K144-PIT-issue/m-p/2086266#M48098</link>
      <description>&lt;P&gt;Hi@&lt;SPAN&gt;vignesh3&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Please refer to the attachment.&lt;/P&gt;
&lt;P&gt;The hardware used is S32K144EVB and the IDE version is S32 Design Studio For Arm V2.2.&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;In fact, I couldn't compile your project from the beginning, and your code directly operated the registers without any instructions. I don't have time to help you check each register one by one, so I made a demo for your reference.&lt;/P&gt;</description>
      <pubDate>Thu, 24 Apr 2025 06:19:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K144-PIT-issue/m-p/2086266#M48098</guid>
      <dc:creator>Senlent</dc:creator>
      <dc:date>2025-04-24T06:19:59Z</dc:date>
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