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    <title>S32KのトピックS32K144 FLEXSPI/LPSPI CS pin</title>
    <link>https://community.nxp.com/t5/S32K/S32K144-FLEXSPI-LPSPI-CS-pin/m-p/917434#M4760</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm using spi_pal demo from SDK&amp;nbsp;S32DS_ARM_v2018.R1.&lt;/P&gt;&lt;P&gt;The master is configured to use FLEXIO SPI.&lt;/P&gt;&lt;P&gt;I have a question related to the CS pin. As you can see on the picture below, the CS is disabled between every bytes.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/84015i0BB9304AA389BF52/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is there a way to enable the CS pin as long as the master has data to transmit?&lt;/P&gt;&lt;P&gt;I looked into the FLEX SPI driver but I'm not familliar with it.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;From Master side (running on another S32k148EVB board), it seems that the LPSPI IRQ is not triggered when the CS is enabled/disabled. I tryed to confirgure the interrupt on PTB0 using&amp;nbsp;INT_SYS_EnableIRQ and&amp;nbsp;INT_SYS_InstallHandler but it seems that it's never triggered.&lt;/P&gt;&lt;P&gt;Aslo the lpspi Callback is not triggered when the CS pin status change.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 28 May 2019 12:45:13 GMT</pubDate>
    <dc:creator>antoine_monmarc</dc:creator>
    <dc:date>2019-05-28T12:45:13Z</dc:date>
    <item>
      <title>S32K144 FLEXSPI/LPSPI CS pin</title>
      <link>https://community.nxp.com/t5/S32K/S32K144-FLEXSPI-LPSPI-CS-pin/m-p/917434#M4760</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm using spi_pal demo from SDK&amp;nbsp;S32DS_ARM_v2018.R1.&lt;/P&gt;&lt;P&gt;The master is configured to use FLEXIO SPI.&lt;/P&gt;&lt;P&gt;I have a question related to the CS pin. As you can see on the picture below, the CS is disabled between every bytes.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/84015i0BB9304AA389BF52/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is there a way to enable the CS pin as long as the master has data to transmit?&lt;/P&gt;&lt;P&gt;I looked into the FLEX SPI driver but I'm not familliar with it.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;From Master side (running on another S32k148EVB board), it seems that the LPSPI IRQ is not triggered when the CS is enabled/disabled. I tryed to confirgure the interrupt on PTB0 using&amp;nbsp;INT_SYS_EnableIRQ and&amp;nbsp;INT_SYS_InstallHandler but it seems that it's never triggered.&lt;/P&gt;&lt;P&gt;Aslo the lpspi Callback is not triggered when the CS pin status change.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 28 May 2019 12:45:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K144-FLEXSPI-LPSPI-CS-pin/m-p/917434#M4760</guid>
      <dc:creator>antoine_monmarc</dc:creator>
      <dc:date>2019-05-28T12:45:13Z</dc:date>
    </item>
    <item>
      <title>Re: S32K144 FLEXSPI/LPSPI CS pin</title>
      <link>https://community.nxp.com/t5/S32K/S32K144-FLEXSPI-LPSPI-CS-pin/m-p/917435#M4761</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This feature is not available in Flexio, but you can use it on LPSPI. Please switch to LPSPI and select continuous mode.&lt;/P&gt;&lt;P&gt;In this mode CS is assert for all frames which are configured in your sending function.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I don't get exactly what are you trying to do with with the next SPI. Why both of them are masters?&amp;nbsp;&lt;/P&gt;&lt;P&gt;If PTB0 is routed to Flexio you can't use it as GPIO.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Razvan&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 29 May 2019 09:49:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K144-FLEXSPI-LPSPI-CS-pin/m-p/917435#M4761</guid>
      <dc:creator>razva_tilimpea</dc:creator>
      <dc:date>2019-05-29T09:49:42Z</dc:date>
    </item>
    <item>
      <title>Re: S32K144 FLEXSPI/LPSPI CS pin</title>
      <link>https://community.nxp.com/t5/S32K/S32K144-FLEXSPI-LPSPI-CS-pin/m-p/917436#M4762</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Yes by changing the master from Flexio to LPSPI we were able to use the continuous mode.&lt;/P&gt;&lt;P&gt;thank you.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 05 Jun 2019 15:57:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K144-FLEXSPI-LPSPI-CS-pin/m-p/917436#M4762</guid>
      <dc:creator>antoine_monmarc</dc:creator>
      <dc:date>2019-06-05T15:57:22Z</dc:date>
    </item>
    <item>
      <title>Re: S32K144 FLEXSPI/LPSPI CS pin</title>
      <link>https://community.nxp.com/t5/S32K/S32K144-FLEXSPI-LPSPI-CS-pin/m-p/917437#M4763</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN class="" style="color: #646464; background-color: #ffffff; border: 0px; font-weight: 200; font-size: 1.286rem; padding: 0px 0px 0px 30px;"&gt;&lt;SPAN class="" style="border: 0px; font-weight: inherit; font-size: 18.004px;"&gt;Hi, Razvan-nicolae,&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" style="color: #646464; background-color: #ffffff; border: 0px; font-weight: 200; font-size: 1.286rem; padding: 0px 0px 0px 30px;"&gt;&lt;SPAN class="" style="border: 0px; font-weight: inherit; font-size: 18.004px;"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" style="color: #646464; background-color: #ffffff; border: 0px; font-weight: 200; font-size: 1.286rem; padding: 0px 0px 0px 30px;"&gt;&lt;SPAN class="" style="border: 0px; font-weight: inherit; font-size: 18.004px;"&gt;I noticed the S32K1xx RM Chapter 52.5.3" For CPHA=1, the select can remain asserted for multiple transfers and the timer status flag can be used to indicate the end of the transfer."&amp;nbsp; Does it mean&amp;nbsp;that it can enable the CS pin as long as the master has data to transmit?&lt;SPAN style="color: #51626f;"&gt;&amp;nbsp;If not, what does it mean?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" style="color: #646464; background-color: #ffffff; border: 0px; font-weight: 200; font-size: 1.286rem; padding: 0px 0px 0px 30px;"&gt;&lt;SPAN class="" style="border: 0px; font-weight: inherit; font-size: 18.004px;"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Thanks, BR,&lt;/P&gt;&lt;P&gt;Han&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Apr 2020 02:10:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K144-FLEXSPI-LPSPI-CS-pin/m-p/917437#M4763</guid>
      <dc:creator>nxf47370</dc:creator>
      <dc:date>2020-04-15T02:10:08Z</dc:date>
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