<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>S32KのトピックS32K322 DMA request</title>
    <link>https://community.nxp.com/t5/S32K/S32K322-DMA-request/m-p/2065482#M47010</link>
    <description>&lt;P&gt;How can I know that if peripherals are requesting to the DMA channel or not ?&lt;/P&gt;</description>
    <pubDate>Thu, 20 Mar 2025 10:13:04 GMT</pubDate>
    <dc:creator>vignesh3</dc:creator>
    <dc:date>2025-03-20T10:13:04Z</dc:date>
    <item>
      <title>S32K322 DMA request</title>
      <link>https://community.nxp.com/t5/S32K/S32K322-DMA-request/m-p/2065482#M47010</link>
      <description>&lt;P&gt;How can I know that if peripherals are requesting to the DMA channel or not ?&lt;/P&gt;</description>
      <pubDate>Thu, 20 Mar 2025 10:13:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K322-DMA-request/m-p/2065482#M47010</guid>
      <dc:creator>vignesh3</dc:creator>
      <dc:date>2025-03-20T10:13:04Z</dc:date>
    </item>
    <item>
      <title>Re: S32K322 DMA request</title>
      <link>https://community.nxp.com/t5/S32K/S32K322-DMA-request/m-p/2065744#M47027</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/238430"&gt;@vignesh3&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;I assume you are trying to check if a DMA transfer has happened? You can configure an interrupt for the following events:&amp;nbsp;&lt;/P&gt;
&lt;OL&gt;
&lt;LI&gt;The major loop is half complete (INTHALF)&lt;/LI&gt;
&lt;LI&gt;The major loop is complete (INTMAJOR)&lt;/LI&gt;
&lt;LI&gt;A configuration error occurs (EEI)&lt;/LI&gt;
&lt;/OL&gt;
&lt;P&gt;You can check with the first two if any major loop has been completed after requesting a transfer. You can also check the CHn_CSR field for the ACTIVE &amp;amp; DONE fields.&amp;nbsp;&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;ACTIVE Status field indicating the channel is currently in execution&lt;/LI&gt;
&lt;LI&gt;DONE Status field indicating major loop completion (cleared by software when a channel begins execution)&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;Please refer to chapter&amp;nbsp;&lt;STRONG&gt;15.5.6 Monitoring transfer descriptor status&lt;/STRONG&gt; from the S32K3XX's Reference Manual as it describes how to monitor the eDMA status.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;BR /&gt;Julián&lt;/P&gt;</description>
      <pubDate>Thu, 20 Mar 2025 17:41:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K322-DMA-request/m-p/2065744#M47027</guid>
      <dc:creator>Julián_AragónM</dc:creator>
      <dc:date>2025-03-20T17:41:42Z</dc:date>
    </item>
    <item>
      <title>Re: S32K322 DMA request</title>
      <link>https://community.nxp.com/t5/S32K/S32K322-DMA-request/m-p/2066015#M47044</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/200831"&gt;@Julián_AragónM&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;&lt;P&gt;I am getting the interrupt but the data not present in the RxBuff array.&lt;/P&gt;&lt;P&gt;can you help me with this I am attaching the code below.&lt;/P&gt;&lt;DIV&gt;void uartRxDmaReqCallBack(void)&lt;/DIV&gt;&lt;DIV&gt;{&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;while(0);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;int main(void)&lt;/DIV&gt;&lt;DIV&gt;{&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; /* Write your code here */&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;//clock init&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;Clock_Ip_Init(Clock_Ip_aClockConfig);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;Siul2_Port_Ip_Init(NUM_OF_CONFIGURED_PINS_PortContainer_0_BOARD_InitPeripherals,g_pin_mux_InitConfigArr_PortContainer_0_BOARD_InitPeripherals);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; IntCtrl_Ip_InstallHandler(DMATCD2_IRQn, uartRxDmaReqCallBack, NULL_PTR);&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; IntCtrl_Ip_EnableIrq(DMATCD2_IRQn);&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; IntCtrl_Ip_Init(&amp;amp;IntCtrlConfig_1);&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; /* init DMA */&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;Dma_Ip_Init(&amp;amp;Dma_Ip_xDmaInitPB);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;/* Initialize DMAMUX via HLD RM driver */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;Rm_Init(&amp;amp;Rm_Config_BOARD_INITPERIPHERALS);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;Lpuart_Uart_Ip_Init(0U,&amp;amp;Lpuart_Uart_Ip_xHwConfigPB_0_BOARD_INITPERIPHERALS);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;Lpuart_Uart_Ip_AsyncReceive(0U,RxBuff,10);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; //S32_NVIC-&amp;gt;ISPR[(uint32)(DMATCD2_IRQn) &amp;gt;&amp;gt; 5U] = (uint32)(1UL &amp;lt;&amp;lt; ((uint32)(DMATCD2_IRQn) &amp;amp; (uint32)0x1FU));&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; for(;;)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; {&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; Siul2_Dio_Ip_WritePin(LED_PORT,LED_PIN,true);&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; delay();&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; Siul2_Dio_Ip_WritePin(LED_PORT,LED_PIN,false);&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; delay();&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; if(exit_code != 0)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; {&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; break;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; }&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; }&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; return exit_code;&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 21 Mar 2025 05:27:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K322-DMA-request/m-p/2066015#M47044</guid>
      <dc:creator>vignesh3</dc:creator>
      <dc:date>2025-03-21T05:27:00Z</dc:date>
    </item>
    <item>
      <title>Re: S32K322 DMA request</title>
      <link>https://community.nxp.com/t5/S32K/S32K322-DMA-request/m-p/2066414#M47071</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/238430"&gt;@vignesh3&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;If DMA is reporting data transfer, but you cannot see it, it may be an issue with the cache. Try adding "&lt;STRONG&gt;__attribute__((section(".mcal_bss_no_cacheable"&lt;/STRONG&gt;&lt;SPAN&gt;&lt;STRONG&gt;)))&lt;/STRONG&gt;" to your Tx and Rx buffers. Also, MPU_ENABLE needs to be added if not included already:&lt;/SPAN&gt;&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;&lt;SPAN&gt;&lt;A href="https://community.nxp.com/t5/S32K/S32K344-eMIOS-triggered-BCTU-ADC-conversion-with-FIFO-and-DMA/m-p/1823659" target="_blank"&gt;Solved: Re: S32K344 – eMIOS triggered BCTU ADC conversion with FIFO and DMA resulting in stale/ no values - NXP Community&lt;/A&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI&gt;&lt;SPAN&gt;&lt;A href="https://community.nxp.com/t5/S32K/UART-sending-by-DMA-has-SBE-error-with-S32K344/td-p/1648304?lightbox-message-images-1656196=224593i2AEC258389C41187" target="_blank"&gt;UART sending by DMA has SBE error with S32K344 - NXP Community&lt;/A&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;&lt;SPAN&gt;Best regards,&lt;BR /&gt;Julián&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 21 Mar 2025 15:25:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K322-DMA-request/m-p/2066414#M47071</guid>
      <dc:creator>Julián_AragónM</dc:creator>
      <dc:date>2025-03-21T15:25:30Z</dc:date>
    </item>
  </channel>
</rss>

