<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: S32K144  IIC communication question in S32K</title>
    <link>https://community.nxp.com/t5/S32K/S32K144-IIC-communication-question/m-p/908064#M4661</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;BR /&gt;There is NACK Detect Flag in the Master Status register MSR[NDF] that is set whenever the master detects a NACK when transmitting an address or data. &lt;BR /&gt;When set, the master will transmit a STOP condition and will not initiate a new START condition until NACK Detect Flag has been cleared.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR, Daniel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 28 May 2019 12:03:16 GMT</pubDate>
    <dc:creator>danielmartynek</dc:creator>
    <dc:date>2019-05-28T12:03:16Z</dc:date>
    <item>
      <title>S32K144  IIC communication question</title>
      <link>https://community.nxp.com/t5/S32K/S32K144-IIC-communication-question/m-p/908063#M4660</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;I want to use the IIC fucntion of mcu s32K144,but I didn't want to use the process expert code&amp;nbsp; to generate IIC function code.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; After I configured these register,and initial the IIC register.I write the 0x04 command and one byte data to register MTDR, according to IIC communication protocal, then I&amp;nbsp;should waite for transmission to end ,and check the ACK of slave device,for the ACK I check all register,and didn't have the ACK flag,so How can I judge the success of this send and start sending the next byte of data?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 27 May 2019 08:26:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K144-IIC-communication-question/m-p/908063#M4660</guid>
      <dc:creator>asd046012</dc:creator>
      <dc:date>2019-05-27T08:26:46Z</dc:date>
    </item>
    <item>
      <title>Re: S32K144  IIC communication question</title>
      <link>https://community.nxp.com/t5/S32K/S32K144-IIC-communication-question/m-p/908064#M4661</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;BR /&gt;There is NACK Detect Flag in the Master Status register MSR[NDF] that is set whenever the master detects a NACK when transmitting an address or data. &lt;BR /&gt;When set, the master will transmit a STOP condition and will not initiate a new START condition until NACK Detect Flag has been cleared.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR, Daniel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 28 May 2019 12:03:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K144-IIC-communication-question/m-p/908064#M4661</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2019-05-28T12:03:16Z</dc:date>
    </item>
    <item>
      <title>Re: S32K144  IIC communication question</title>
      <link>https://community.nxp.com/t5/S32K/S32K144-IIC-communication-question/m-p/908065#M4662</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;When IIC communciation occur error for sending address and data,The NACK flag will be detected,but this flag can't be the ending flag of&amp;nbsp; sending data and address.I want to know that after send a data or address, I should check which register bit?&amp;nbsp; &amp;nbsp;and how I judge that this sending action has been finished,and I can send the next data.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 29 May 2019 11:12:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K144-IIC-communication-question/m-p/908065#M4662</guid>
      <dc:creator>asd046012</dc:creator>
      <dc:date>2019-05-29T11:12:57Z</dc:date>
    </item>
    <item>
      <title>Re: S32K144  IIC communication question</title>
      <link>https://community.nxp.com/t5/S32K/S32K144-IIC-communication-question/m-p/908066#M4663</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;There is no such bit, you can fill the transmit FIFO with commands and data and expect ACK. "Multiple transmit and receive commands can be inserted between the START condition&amp;nbsp;and STOP conditon; transmit and receive commands must not be interleaved..." (50.4.2.1 RM rev.9).&lt;/P&gt;&lt;P&gt;If NACK is received,&amp;nbsp;the master will&amp;nbsp;transmit a STOP condition and will not initiate a new START condition until NACK Detect Flag has been&amp;nbsp;cleared.&amp;nbsp;The transfer is complete when a Stop condition has been generated.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/84311iF422A27DBF42B6B8/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/84312iD381A7587F5A222B/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Daniel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 31 May 2019 11:44:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K144-IIC-communication-question/m-p/908066#M4663</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2019-05-31T11:44:18Z</dc:date>
    </item>
    <item>
      <title>Re: S32K144  IIC communication question</title>
      <link>https://community.nxp.com/t5/S32K/S32K144-IIC-communication-question/m-p/908067#M4664</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; If I can check like this:after transfer a data,I check the bit TDF of register MSR,if the bit TDF is set as 1,I will think the transfer action has end?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;I inintail the IIC function as below sequence:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;uint32_t tmp = 0x00000000;&lt;BR /&gt; IIC_DRIVER_BASE-&amp;gt;MCR = 0x00000002;&lt;BR /&gt; Delay_20us();&lt;BR /&gt; /**disable IIC**/&lt;BR /&gt; IIC_DRIVER_BASE-&amp;gt;MCR = 0x00000000;&lt;BR /&gt; IIC_DRIVER_BASE-&amp;gt;MSR = 0x00000000;&lt;BR /&gt; /***set clock Prescaler and diable match fucntion&lt;BR /&gt; ***set pin fucntion and NACK&lt;BR /&gt; ***/ &lt;BR /&gt; IIC_DRIVER_BASE-&amp;gt;MCFGR1 = 0x00000000;&lt;BR /&gt; /**set baud 100K**/&lt;BR /&gt; IIC_DRIVER_BASE-&amp;gt;MCCR0 = 0x0D1A1A34;&lt;BR /&gt; /***disable all IIC interrupt**/ &lt;BR /&gt; IIC_DRIVER_BASE-&amp;gt;MIER = 0x00000000;&lt;BR /&gt; /**disable IIC DMA Fucntion**/&lt;BR /&gt; IIC_DRIVER_BASE-&amp;gt;MDER = 0x00000000;&lt;/P&gt;&lt;P&gt;IIC_DRIVER_BASE-&amp;gt;MCFGR0 = 0x00000000;&lt;BR /&gt; IIC_DRIVER_BASE-&amp;gt;MCFGR2 = 0x00000000;&lt;BR /&gt; IIC_DRIVER_BASE-&amp;gt;MCFGR3 = 0x00000000;&lt;BR /&gt; IIC_DRIVER_BASE-&amp;gt;MDMR = 0x00000000;&lt;BR /&gt; IIC_DRIVER_BASE-&amp;gt;MCCR1 = 0x00000000;&lt;BR /&gt; IIC_DRIVER_BASE-&amp;gt;MFCR = 0x00000000;&lt;/P&gt;&lt;P&gt;/**enable IIC**/&lt;BR /&gt; tmp = (uint32_t)IIC_DRIVER_BASE-&amp;gt;MCR;&lt;BR /&gt; tmp &amp;amp;= (uint32_t)(~(LPI2C_MCR_MEN_MASK));&lt;BR /&gt; tmp |= LPI2C_MCR_MEN(0x00000001);&lt;BR /&gt; IIC_DRIVER_BASE-&amp;gt;MCR = tmp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;after executing the sequence,the valeu of register MSR is alway 0x02000001,so I can solve this issue?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 03 Jun 2019 02:28:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K144-IIC-communication-question/m-p/908067#M4664</guid>
      <dc:creator>asd046012</dc:creator>
      <dc:date>2019-06-03T02:28:35Z</dc:date>
    </item>
    <item>
      <title>Re: S32K144  IIC communication question</title>
      <link>https://community.nxp.com/t5/S32K/S32K144-IIC-communication-question/m-p/908068#M4665</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;The MSR[TDF] flag is set whenever&amp;nbsp;the number of words in the transmit FIFO is equal or less than&amp;nbsp;TXWATER.&lt;/P&gt;&lt;P&gt;But all&amp;nbsp;transfers&amp;nbsp;begin with a START&amp;nbsp;condition and are terminated by a STOP stop condition.&lt;/P&gt;&lt;P&gt;And there is a flag&amp;nbsp;MSR[SDF] that is set whenever the master generates a STOP.&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.nxp.com/docs/en/user-guide/UM10204.pdf"&gt;UM10204&amp;nbsp;I2C-bus specification and user manual&lt;/A&gt;.&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-342048"&gt;Example_S32K144_I2C_Master_MPL3115A2_S32DSR1_v3&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR, Daniel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 03 Jun 2019 11:41:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K144-IIC-communication-question/m-p/908068#M4665</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2019-06-03T11:41:42Z</dc:date>
    </item>
  </channel>
</rss>

