S32KのトピックRe: S32K388: Configuring additional lockstep cores

S32K388: Configuring additional lockstep cores

darknite2023 — Wed, 19 Feb 2025 01:14:01 GMT

Hi. How do I go about configuring S32K388's split cores (core 2 and core 3) into a lockstep pair? Does this need to be done via DCF records or can I do it dynamically?

Regards.

Re: S32K388: Configuring additional lockstep cores

Robin_Shen — Wed, 19 Feb 2025 06:14:25 GMT

According to the Figure 10. Block diagram – S32K388, Core 2 is Permanent Lock-Step.

Best Regards,
Robin
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Re: S32K388: Configuring additional lockstep cores

darknite2023 — Thu, 20 Feb 2025 01:59:00 GMT

Hi. Thanks for providing that info/reference.

This info does not match what the S32K3XX Ref Man has to say when looking at the value of DCM_GPR.DCMROF19 register @ address 0x402AC348. The contents of that register is 0x60000000 which indicates:

DCM DONE
LOCKSTEP EN on M7_Core0 and M7_Core1

So, if it is indeed Core CM2_7 that is permanently in lockstep mode, how can I verify that - which register can provide that info?

Assuming Core CM7_2 is in lockstep mode, how can I configure Cores CM7_0 and CM7_1 to be in lockstep mode? Can I do this dynamically? If so, how?

Regards.

Re: S32K388: Configuring additional lockstep cores

Robin_Shen — Thu, 20 Feb 2025 06:47:50 GMT

CM7_0 and CM7_1 of S32K388 can be configured by modifying LOCKSTEP_EN of DCF record to:
0b - Decoupled operation of Cortex-M7_0 and Cortex-M7_1
1b - Lockstep operation of Cortex-M7_0 and Cortex-M7_1
However, CM7_2 and CM7_3 of S32K388 perform similar operations.
For specific methods, please refer to: Example_S32K344_decouple_RTD400_Ip_C40_DS35

Re: S32K388: Configuring additional lockstep cores

darknite2023 — Thu, 20 Feb 2025 18:08:13 GMT

Thanks.

I understand that it needs to be enabled via DCF. My question however is regarding the discrepancy between what S32K3XX Ref Manual has with regards to the diagram that shows S32K388 Core CM7_2 in permanent lockstep state while the contents of DCM_GPR.DCMROF19 register @ address 0x402AC348 is 0x60000000 thus indicating that lockstep is enabled on cores M7_Core0 and M7_Core1!

Regards.

Re: S32K388: Configuring additional lockstep cores

Robin_Shen — Tue, 25 Feb 2025 04:25:16 GMT

Sorry I didn't understand your question.
Didn't you originally ask about Core 2(CM7_2) and Core 3(CM7_3)?

DCM_GPR.DCMROF19 has nothing to do with Core 2(CM7_2) and Core 3(CM7_3). There is no register that reflects the status of Core 2(CM7_2) and Core 3(CM7_3) because their status is fixed.

As you can see in Figure 10. Block diagram – S32K388.png, only CM7_0 and CM7_1 can be switched between Lockstep and Decoupled.

DCM_GPR.DCMROF19 only reflects the status of Core 0(CM7_0) and Core 1(CM7_1).

NOTE: The reset value is undefined on reset and is loaded from the flash memory contents at the end of the reset sequence.

The S32K388 core consists of two types:
1x LS Cortex-M7 + 3xCortex-M7 @ 320MHz or
2x LS Cortex-M7 + 1xCortex-M7 @ 320MHz