https://community.nxp.com/t5/S32K/S32K344-STCU-BIST-quest/m-p/2044460#M45911 <P>Hi&nbsp;NXP，</P><P>1. Why does the S32K344 run Bist_Run(BIST_SAFETYBOOT_CFG) into Hardfault?</P><P>2.&nbsp;<SPAN>I am using standby RAM to store data, does this affect BIST?</SPAN></P><P><SPAN>Best Regards,</SPAN><BR /><SPAN>Li 3</SPAN></P> Fri, 14 Feb 2025 09:44:06 GMT li3 2025-02-14T09:44:06Z https://community.nxp.com/t5/S32K/S32K344-STCU-BIST-quest/m-p/2044460#M45911 <P>Hi&nbsp;NXP，</P><P>1. Why does the S32K344 run Bist_Run(BIST_SAFETYBOOT_CFG) into Hardfault?</P><P>2.&nbsp;<SPAN>I am using standby RAM to store data, does this affect BIST?</SPAN></P><P><SPAN>Best Regards,</SPAN><BR /><SPAN>Li 3</SPAN></P> Fri, 14 Feb 2025 09:44:06 GMT https://community.nxp.com/t5/S32K/S32K344-STCU-BIST-quest/m-p/2044460#M45911 li3 2025-02-14T09:44:06Z https://community.nxp.com/t5/S32K/S32K344-STCU-BIST-quest/m-p/2045962#M45986 <P>Hi&nbsp;<SPAN>Li 3,</SPAN></P> <P>BIST will reset FCCU and reset SRAM content, thus SRAM ECC need be re-initialized after ST_DONE functional reset. &nbsp;Considering that you use standby RAM, please check if the hardfault is a <A href="https://community.nxp.com/t5/S32K-Knowledge-Base/How-To-Debug-A-Fault-Exception-On-ARM-Cortex-M-V7M-MCU-S32K3XX/ta-p/1595570" target="_self">Busfault</A>&nbsp;caused by the ECC RAM not being initialized.</P> <P>Have you checked the <STRONG>ERR_STAT</STRONG> register?</P> <P>By the way: The discussion in <A href="https://community.nxp.com/t5/S32K/STCU2-internal-errors-and-SPD-BIST-BIST-DIAGNOSTIC-CFG/m-p/1813872" target="_self">STCU2 internal errors and SPD-BIST BIST_DIAGNOSTIC_CFG</A> may be helpful</P> <P>Best Regards,<BR />Robin</P> Tue, 18 Feb 2025 05:24:30 GMT https://community.nxp.com/t5/S32K/S32K344-STCU-BIST-quest/m-p/2045962#M45986 Robin_Shen 2025-02-18T05:24:30Z