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    <title>S32KのトピックS32Kxx SDK example issue</title>
    <link>https://community.nxp.com/t5/S32K/S32Kxx-SDK-example-issue/m-p/2042641#M45843</link>
    <description>&lt;P&gt;Hi,&amp;nbsp;&lt;BR /&gt;&lt;BR /&gt;I am trying to run some basic examples on an FS32K144HAT0MLFT that I have on a custom board. I installed the&amp;nbsp;&lt;EM&gt;S32 Design Studio for ARM 2.2 Update 1 S32 SDK for S32K1xx SR RTM 3.0.3&amp;nbsp;&lt;/EM&gt;and wanted to run the CAN 2.0 example. The example builds without issues, but the problem is in the &lt;STRONG&gt;SPLL_init_160MHz(void)&amp;nbsp;&lt;/STRONG&gt;function. When I step through the debugger the execution gets stuck on this line, looping endlessly:&lt;/P&gt;&lt;LI-CODE lang="c"&gt;while(!(SCG-&amp;gt;SPLLCSR &amp;amp; SCG_SPLLCSR_SPLLVLD_MASK)); /* Wait for SPLL valid */&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;This is the whole function:&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;LI-CODE lang="c"&gt;void SPLL_init_160MHz(void) {
while(SCG-&amp;gt;SPLLCSR &amp;amp; SCG_SPLLCSR_LK_MASK); /* Ensure SPLLCSR unlocked */
SCG-&amp;gt;SPLLCSR = 0x00000000; /* SPLLEN=0: SPLL is disabled (default) */
SCG-&amp;gt;SPLLDIV = 0x00000302; /* SPLLDIV1 divide by 2; SPLLDIV2 divide by 4 */
SCG-&amp;gt;SPLLCFG = 0x00180000; /* PREDIV=0: Divide SOSC_CLK by 0+1=1 */
/* MULT=24: Multiply sys pll by 4+24=40 */
/* SPLL_CLK = 8MHz / 1 * 40 / 2 = 160 MHz */
while(SCG-&amp;gt;SPLLCSR &amp;amp; SCG_SPLLCSR_LK_MASK); /* Ensure SPLLCSR unlocked */
SCG-&amp;gt;SPLLCSR = 0x00000001; /* LK=0: SPLLCSR can be written */
/* SPLLCMRE=0: SPLL CLK monitor IRQ if enabled */
/* SPLLCM=0: SPLL CLK monitor disabled */
/* SPLLSTEN=0: SPLL disabled in Stop modes */
/* SPLLEN=1: Enable SPLL */

while(!(SCG-&amp;gt;SPLLCSR &amp;amp; SCG_SPLLCSR_SPLLVLD_MASK)); /* Wait for SPLL valid */
}&lt;/LI-CODE&gt;&lt;P&gt;The example is the same one found in the "AN5413 - S32K1xx Series Cookbook - Application Note, 2.9 CAN 2.0"&amp;nbsp;&lt;BR /&gt;&lt;BR /&gt;Could that have something to do with the particular version of the S32K144 microcontroller? I am receiving the S32K144 EVB soon and I'll try it on that one as well. My primary need is to have CAN 2.0 Extended working.&amp;nbsp;&lt;BR /&gt;If there are some other examples better suited for this, I'd be happy to try them.&lt;BR /&gt;&lt;BR /&gt;Thanks in advance!&lt;/P&gt;</description>
    <pubDate>Wed, 12 Feb 2025 13:48:22 GMT</pubDate>
    <dc:creator>vladimirk</dc:creator>
    <dc:date>2025-02-12T13:48:22Z</dc:date>
    <item>
      <title>S32Kxx SDK example issue</title>
      <link>https://community.nxp.com/t5/S32K/S32Kxx-SDK-example-issue/m-p/2042641#M45843</link>
      <description>&lt;P&gt;Hi,&amp;nbsp;&lt;BR /&gt;&lt;BR /&gt;I am trying to run some basic examples on an FS32K144HAT0MLFT that I have on a custom board. I installed the&amp;nbsp;&lt;EM&gt;S32 Design Studio for ARM 2.2 Update 1 S32 SDK for S32K1xx SR RTM 3.0.3&amp;nbsp;&lt;/EM&gt;and wanted to run the CAN 2.0 example. The example builds without issues, but the problem is in the &lt;STRONG&gt;SPLL_init_160MHz(void)&amp;nbsp;&lt;/STRONG&gt;function. When I step through the debugger the execution gets stuck on this line, looping endlessly:&lt;/P&gt;&lt;LI-CODE lang="c"&gt;while(!(SCG-&amp;gt;SPLLCSR &amp;amp; SCG_SPLLCSR_SPLLVLD_MASK)); /* Wait for SPLL valid */&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;This is the whole function:&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;LI-CODE lang="c"&gt;void SPLL_init_160MHz(void) {
while(SCG-&amp;gt;SPLLCSR &amp;amp; SCG_SPLLCSR_LK_MASK); /* Ensure SPLLCSR unlocked */
SCG-&amp;gt;SPLLCSR = 0x00000000; /* SPLLEN=0: SPLL is disabled (default) */
SCG-&amp;gt;SPLLDIV = 0x00000302; /* SPLLDIV1 divide by 2; SPLLDIV2 divide by 4 */
SCG-&amp;gt;SPLLCFG = 0x00180000; /* PREDIV=0: Divide SOSC_CLK by 0+1=1 */
/* MULT=24: Multiply sys pll by 4+24=40 */
/* SPLL_CLK = 8MHz / 1 * 40 / 2 = 160 MHz */
while(SCG-&amp;gt;SPLLCSR &amp;amp; SCG_SPLLCSR_LK_MASK); /* Ensure SPLLCSR unlocked */
SCG-&amp;gt;SPLLCSR = 0x00000001; /* LK=0: SPLLCSR can be written */
/* SPLLCMRE=0: SPLL CLK monitor IRQ if enabled */
/* SPLLCM=0: SPLL CLK monitor disabled */
/* SPLLSTEN=0: SPLL disabled in Stop modes */
/* SPLLEN=1: Enable SPLL */

while(!(SCG-&amp;gt;SPLLCSR &amp;amp; SCG_SPLLCSR_SPLLVLD_MASK)); /* Wait for SPLL valid */
}&lt;/LI-CODE&gt;&lt;P&gt;The example is the same one found in the "AN5413 - S32K1xx Series Cookbook - Application Note, 2.9 CAN 2.0"&amp;nbsp;&lt;BR /&gt;&lt;BR /&gt;Could that have something to do with the particular version of the S32K144 microcontroller? I am receiving the S32K144 EVB soon and I'll try it on that one as well. My primary need is to have CAN 2.0 Extended working.&amp;nbsp;&lt;BR /&gt;If there are some other examples better suited for this, I'd be happy to try them.&lt;BR /&gt;&lt;BR /&gt;Thanks in advance!&lt;/P&gt;</description>
      <pubDate>Wed, 12 Feb 2025 13:48:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32Kxx-SDK-example-issue/m-p/2042641#M45843</guid>
      <dc:creator>vladimirk</dc:creator>
      <dc:date>2025-02-12T13:48:22Z</dc:date>
    </item>
    <item>
      <title>Re: S32Kxx SDK example issue</title>
      <link>https://community.nxp.com/t5/S32K/S32Kxx-SDK-example-issue/m-p/2043722#M45887</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/192379"&gt;@vladimirk&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;This example is designed to be used with two EVBs connected together, if you only have one device you can try with the examples that are configured in loopback in the latest software versions for example S32DS 3.5 and RTD 2.0.0.&lt;/P&gt;
&lt;P&gt;Note: We recommend working with these latest software versions, as previous versions may contain bugs that have been fixed in more recent releases.&lt;/P&gt;
&lt;P&gt;BR,&lt;BR /&gt;IsaulO.&lt;/P&gt;</description>
      <pubDate>Thu, 13 Feb 2025 18:14:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32Kxx-SDK-example-issue/m-p/2043722#M45887</guid>
      <dc:creator>IsaulO</dc:creator>
      <dc:date>2025-02-13T18:14:33Z</dc:date>
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