S32K146 IC Memory Protection Unit

shlee2872 — Tue, 28 Jan 2025 14:31:25 GMT

I accessed unallowed memory range (0x1FFEF654, which is out of memory range)

But I couldnt' the MPU Error Information in S32K146 MCU by checking Trace32 Debugger.

So I checked Arm CM4 Registers and then the checked Information is like below these informations.

// S32K146 MCU's MPU

All of SPER# is 0 (No Error Occurred)

EADDR is 0

But the MPU in MCU is enabled.

/// ARM CM4 Reg Value //

Memory Protection Unit

MPU_TYPE : 00000000 /IREGION: 0 /DREGION:0 /SEPERATE: Not Supported

MPU_CTRL: 00000000 /PRIVDEFENA: Disabled HFMINEA: MPU Disabled /ENABLE: Disabled

MPU_RNR: 00000000 /REGION:00

=> So I checked MPU in Arm core is disabled.

But the other register values are below things.

MMFAR : 1FFEF654 (out of memory range in S32K146)

MMFSR is Initialized Values (Not Valid, Not Active, Not Occurred)

BFSR

- BFARVALID: Valid / PRECISERR: Occurred

BFAR : 1FFEF654 (out of memory range in S32K146)

HFSR

- Forced : Occurred / DEBEUGEV, VECTTBL : Not Occurred

=> So I think Bus Fault Handler makes MemManageFault Escalate to Hard Fault.

But I can't understand how MPU in Arm Core is not activated makes MemManage Fault?

If XN Region accessed makes this situation, I think IACCVIOL in MMFSR Should be Occurred

because It is not clear by another exception handler like MMARVALID in MMFSR.

Would you explain this situations and would you offer the algorithm of how accessing to

out of memory range leads to hard fault handler?

Thank you for your support.

Re: S32K146 IC Memory Protection Unit

danielmartynek — Wed, 29 Jan 2025 08:42:30 GMT

The ARM Cortex M4 core MPU is not implemented on the S32K14x series.

There is NXP MPU implemented on the bus instead.

You need to configure the NXP MPU first.

Any violation of the NXP MPU results in a bus fault that is routed to the ARM BusFault exception.

This fault is excalated to HardFault if the BusFault exception is disabled.

Regardless of the MPU, there is always a bus fault detected if not-implemented memory is accessed though.

Refer to this example:

Regards,

Daniel