S32KのトピックRe: ADC cross triggering

ADC cross triggering

Ayaz — Fri, 24 Jan 2025 12:27:34 GMT

Hi,

I am working on a project involving cross-triggering with a 12-channel ADC signal, but I’m encountering issues with the signals not being in the correct order. Here is my current design:

eMOIS_CH1: Offset by 2 µs → ADC1 → Signal 1 & Signal 2
eMOIS_CH2: Offset by 4.2 µs → ADC2 → Signal 3 & Signal 4
eMOIS_CH3: Offset by 7.2 µs → Cross-triggering → ADC0 & ADC2 → Signal 5 to Signal 16
The watermark value is set to 16. Every time the FIFO interrupt occurs, I expect to receive the FIFO values in the following order:

Signal 1 & Signal 2
Signal 3 & Signal 4
For the cross-triggering:

Signal 5(ADC0_P2)& Signal 6(ADC2_P2)
Signal 7(ADC0_P6)& Signal 8(ADC2_P6)
Signal 9(ADC0_S14)& Signal 10(ADC2_S14)
Signal 11(ADC0_S15)& Signal 12(ADC2_S15)
Signal 13(ADC0_S10)& Signal 14(ADC2_S10)
Signal 15(ADC0_S16)& Signal 16(ADC2_S16)
However, the signals for cross-triggering are not arriving in the correct order. Could you please provide guidance on how to resolve this issue?

I can trigger each ADC instance simultaneously using separate eMIOS channels, but this requires adding one more eMIOS channel for triggering. In my current design, I have implemented “cross-triggering,” which results in some values in my FIFO that I do not need to use.

Could you please provide suggestions for designing these 12 signals more efficiently?
I have attached my project so you can get a better understanding of the design.

Re: ADC cross triggering

PetrS — Mon, 27 Jan 2025 13:51:52 GMT

Hi,

seems a BCTU list setting does not correspond to your description. I see just 5 pairs for parallel sampling, not 6. So Watermark should be set to 13 for this BCTU list.

BR, Petr

Re: ADC cross triggering

Ayaz — Tue, 28 Jan 2025 08:06:04 GMT

Hi
I have modified the watermark value to 13, but still, the signals are not coming in the right order ?

Re: ADC cross triggering

PetrS — Tue, 28 Jan 2025 15:21:30 GMT

Hi,

I tested your code and it gives me steady order of results in FIFO, only standard channels seems to be swapped

Checking your code I found you enabled presampling for some channels in each ADC modules, but this does not correspond with channels actually sampled by BCTU. After below modification the order of standard channels is correct.

BR, Petr

Re: ADC cross triggering

Ayaz — Tue, 28 Jan 2025 16:01:15 GMT

Hi
Thanks for the info,
but these signals are missing
Signal 6(ADC2_P2)
Signal 7(ADC0_P6)
Signal 10(ADC2_S14)
Signal 11(ADC0_S15)
Signal 14(ADC2_S10)
Signal 15(ADC0_S16)
Since I am implementing cross-triggering for ADC0 and ADC2, I assume that I will sample the same signal on ADC0 and ADC2 simultaneously. For example, when channel Signal 6 (P2) is triggered, I should get two results: one from ADC0_P2 and one from ADC2_P2, both stored in the FIFO.
what do i miss here ?

Re: ADC cross triggering

PetrS — Wed, 29 Jan 2025 08:28:50 GMT

Hi,

there is no signal missing, FIFO contains all samples specified in the BCTU list.
Seems you only misinterpreted its behavior in case of multiple parallel conversion. The RM outlines this

BR, Petr