topic code can not get data from no_cacheable ram if source code runs in ITCM in S32K

code can not get data from no_cacheable ram if source code runs in ITCM

yin_qiu — Mon, 20 Jan 2025 11:15:43 GMT

hello NXP experts:

I met a question about RAM access.

I modify the link file and locate all the source code in ITCM (all the hex is located from 0x00000000) and I take use of SPI and DMA to communicate with the external device.

when I set the value in global ram and trigger DMA transmit, there is no data in MTSR PIN， if I set a breakpoint after RAM data setting but before DMA transfer. there will be data in MTSR.

so I guess the root cause may be the ram refresh because ITCM runs high frequency than SRAM .

you can check the two pic below, if I go from breakpoint 1 to breakpoint 2 ,there is no contents in the MTSR(orange color)

you can check the two pictures below and if I go from breakpoint 1 to breakpoint 2 to breakpoint 3(I just do a stop between breakpoint 1 and breakpoint 3) .

there is contents in the MTSR(orange color).

do you have any solution for this problem .thanks a lot

Re: code can not get data from no_cacheable ram if source code runs in ITCM

PetrS — Tue, 21 Jan 2025 14:27:38 GMT

Hi,

seems the buffer is simple not placed in non cacheable area. If not, flush a cache by calling Cache Clean function before SPI transmit.

BR, Petr

Re: code can not get data from no_cacheable ram if source code runs in ITCM

yin_qiu — Tue, 04 Feb 2025 12:33:44 GMT

hi PetrS：

I set the Tx buffer and Rx buffer in the no cacheable ram, it works OK if the source code runs in PFlash

but if I set the code run in ITCM by modify the link file, the SPI seems can not transfer the correct data in MTSR.

I try to solve this problem by init the Tx buffer by data segment rather than bss segment and it works OK because there is no need to init the tx buffer before calling "SPI_SetupEB".

but I still meet a question for getting data in Rx Buffer. sometimes ,I can not get the correct data from Rx buffer event if the contents in MRST pin is correct.(the contents in MRST is 1 but the data in Rx Buffer in 0, but correct 1 is get if a break point is set)

Re: code can not get data from no_cacheable ram if source code runs in ITCM

yin_qiu — Wed, 05 Feb 2025 06:35:49 GMT

hi PetrS:

in my current project, I disable the MPU function by disable the data setting for "S32_MPU->CTRL " in "system.c".

Will it have any relationship with the current problem?

Re: code can not get data from no_cacheable ram if source code runs in ITCM

yin_qiu — Wed, 05 Feb 2025 08:12:09 GMT

hi PetrS:

I think I have solved this problem :

because I have to put all source code in RAM and ITCM and DTCM is not large enough to cover all the source code ,so I put some code in shareable ram. but it will report hard fault if instruction access in shareable ram.

I tried to solve this hardfault problem by disable the MPU. but disable the MPU may have some effect on the other area for example no cacheable ram .

now I try to enable MPU again but modify the rasr register for shareable ram and change the value from 0x130C0001UL to 0x030C0001UL