topic Re: ADC TEST in S32K

ADC TEST

Ayaz — Thu, 16 Jan 2025 15:17:26 GMT

Hi
I have designed the BCTU to receive triggers from eMIOS, which have been offset in the following way:

I need to sample the signals at 40kHz.

eMIOS CH1: Offset by 2µs
- Signal 1
- Signal 2
eMIOS CH2: Offset by 4.5µs after the conversion for CH1 is completed
- Signal 1
- Signal 2
eMIOS CH3: Offset by 7.2µs after the conversion for CH2 is completed
- Signal 1
  to
- Signal 6
eMIOS CH4: Offset by 7.2µs after the conversion for CH2 is completed
- Signal 1
  to
- Signal 6
  
  I have offset the trigger based on the time required for each ADC signal conversion with pre-sampling. The calculation time for sampling has been determined based on the image below.
  Now, I need to ensure that the signals are not overlapping and that I am reading all the signals correctly. To achieve this, I have plotted the BCTU_trigger and the FIFO interrupts on an oscilloscope. This allows me to visually verify all 16 signal samples before the FIFO1 interrupts within 25µs (40kHz). However, the issue is that I can only see 6 triggers out of the 16, as shown in the images below.
  - The orange represents the signals.
  - The blue represents the FIFO interrupts.
  I wonder what I might have missed here. I believe the timing may be incorrect. If you can assist me in finding solutions for this, I have attached my project
  * S32K344
  * RTD 5.0.0

Re: ADC TEST

Senlent — Fri, 17 Jan 2025 08:46:48 GMT

Hi@Ayaz

ADC conversion Time Example:

In your project, 16 channels are sampled, and the ST is 22 cycle.

Total_conversion_time = [(0+22+(4 *13)+2)*16]+1 = 1217cycles ~= 15.2125us

Also you delay time is 2us + 4.5us + 7.2us = 13.7us

So the whole time cost is : 15.2125us + 13.7us = 28.9125us.

And your PWM frequence is 40KHz which is 25us.

So do you think this is feasible?

Re: ADC TEST

Ayaz — Fri, 17 Jan 2025 10:14:26 GMT

Hi,

Thanks for the info. I think there might have been a misunderstanding regarding the design. The image below shows how we have designed the BCTU.

ADC Sample Time 23: As shown in the previous image, we are performing pre-sampling.
CH3 and CH4: These channels are triggered simultaneously.
Yellow Label: This indicates the offset timing for each trigger.

we are doing the pre-sampling and The CH3 and CH4 are triggered at the same time.

The Yalow label presents the offset timing for each trigger
--offset 2us--> eMIOS CH1
--------offset 4,5us----> eMIOS CH2
--------------offset 7,2us---------> eMIOS CH3
--------------offset 7,2us---------> eMIOS CH4

Theoretically, the design should work, but it is not working in practice.

Re: ADC TEST

Senlent — Mon, 20 Jan 2025 07:10:50 GMT

Hi@Ayaz

I changed the BCTU trigger and I can get the correct sampling order in FIFO.

But I can't get the correct BCTU Trigger notification unless I reduce the trigger frequency and increase the ADC ST.

I have reported this problem to our internal forum, maybe they can tell me the reason.

Re: ADC TEST

Ayaz — Mon, 20 Jan 2025 09:57:12 GMT

Hi@Senlent
Thanks for the info.You have disabled CH4 for triggering the second group for ADC2, which I want to keep triggering separately.
I have some questions about the changes you provided:
1 ) What is the reason for changing the ADC calibration prescaler from 4 to 1 ?

To --->>

2 ) What is the reason for removing the self-test from the ADC configurations?
3) Can you explain the changes you made to the PWM triggers, phase shift, duty cycle, and trigger? What is different between the one I made and the one you provided? What value does that provide?

4 ) You have also changed the sequence of these triggers according to the ADCs. Does it need to be from ADC0 to ADC2?

5 ) When you say “BCTU Trigger notification,” do you mean trigger notifications? I just need to be sure.

6 ) Is there a difference in sampling time between sampling the precision ADC pins and the standard ones?

The main purpose of this test is to ensure that all signals are read correctly without overlapping. Additionally, it aims to offset the triggering of ADC1 and ADC2 so that each signal is sampled while other ADC conversions are off, thereby achieving the best ADC reading performance.
But if I can't get the correct BCTU Trigger notification, so it not possible to do perform this test .
7 ) Is there another way to perform this test?
I would really appreciate it if you could answer all my questions

Re: ADC TEST

Senlent — Tue, 21 Jan 2025 06:44:48 GMT

Hi@Ayaz

1 ) What is the reason for changing the ADC calibration prescaler from 4 to 1 ?

2 ) What is the reason for removing the self-test from the ADC configurations?

I actually changed these to test the effect on "BCTU_Trigger". You can ignore these changes.

3) Can you explain the changes you made to the PWM triggers, phase shift, duty cycle, and trigger? What is different between the one I made and the one you provided? What value does that provide?

These modifications are made to facilitate my observation of the trigger timing.

4 ) You have also changed the sequence of these triggers according to the ADCs. Does it need to be from ADC0 to ADC2?

Your project uses two channels to trigger two ADC instances simultaneously. In fact, this can be achieved by triggering with one channel. Of course, you can ignore these changes.

5 ) When you say “BCTU Trigger notification,” do you mean trigger notifications? I just need to be sure.

yes, in your project is "BCTU_Trigger"

6 ) Is there a difference in sampling time between sampling the precision ADC pins and the standard ones?

No different as i know.

7 ) Is there another way to perform this test?

The attached is my modified demo, with only the following two changes.

You can read the exact ADC value in "sFifoData" and the order of each channel is as expected.

So far, the only problem is that the triggering of "void BCTU_Trigger(void)" does not meet my expectations. I have reported this problem to the internal forum. You can treat it as a bug.

I will reply to you by private message after getting the explanation from the internal forum.