topic Re: PWM_BCTU_ADC in S32K

PWM_BCTU_ADC

Ayaz — Tue, 10 Dec 2024 16:49:31 GMT

Hi
I am currently designing an ADC reading system where I trigger the BCTU using PWM flags in OPWMT mode. I have set up three triggers for the BCTU, each offset to ensure that signals are sampled sequentially and stored in the FIFO in the correct order. This way, I can be certain that the data in FIFO[0] corresponds to the first signal, FIFO[1] to the second signal, and FIFO[2] to the third signal.

The setup is as follows:

PWM Trigger CH3 —> BCTU —> ADC 0
PWM Trigger CH1 —> BCTU —> ADC 1
PWM Trigger CH2 —> BCTU —> ADC 2

I have designed my ADC reading system as described, but the signals are not appearing in the correct order. Could you please assist me with this issue? I have attached my project.

Re: PWM_BCTU_ADC

Ayaz — Tue, 10 Dec 2024 23:51:22 GMT

2) for OPMMT mode , to calculate the offset .
Offset in ticks = core clock * time (us) . But the trigger start from 1 .
My question is is the the formula above should be +1 or -1 ??

Re: PWM_BCTU_ADC

Ayaz — Wed, 11 Dec 2024 08:32:35 GMT

Additional Information :
S32K344
RTD 5.0.0

Re: PWM_BCTU_ADC

Senlent — Thu, 12 Dec 2024 09:23:25 GMT

Hi@Ayaz

I'm sorry, I'm dealing with your problem, but it will take me some time to figure out the reason, please be patient

Re: PWM_BCTU_ADC

Ayaz — Wed, 11 Dec 2024 10:37:40 GMT

Hi @Senlent ,

I would like to know the order of signals that is stored in the BCTU FIFO considering trigger offsets.

ADC0 signals are grouped together and a single trigger triggers it (no cross triggering). The same is done with ADC1 and ADC2.

Now, since I have offset the triggers, I would expect that the BCTU FIFO is filled in the order of the offset.

Consider the example that I sent you (all in OPWMT mode):

EMIOS_0_3 has an offset value of 1

EMIOS_0_1 has an offset of 312

EMIOS_0_2 has an offset of 416

Here is my BCTU configuration

When I plotted the eMIOS trigger I can see the trigger offset on the oscilloscope.

Considering that the BCTU FIFO is empty at the start, I expect that the EMIOS_0_3 will be the first to generate a trigger to the BCTU. The signals ADC0_A_RD and ADC0_B_RD will be sampled first and will be filled in the BCTU FIFO[0] and BCTU FIFO[1].

The next trigger will be EMIOS_0_1 and will sample the signals ADC1_A and ADC1_B. These 2 values will be stored in the BCTU FIFO[2] and BCTU FIFO[3] respectively.

Finally the last trigger EMIOS_0_2 which will sample ADC2_A and ADC2_B and store it in BCTU FIFO[2] and BCTU FIFO[3] respectively.

But when I read the first 6 BCTU FIFO values using Bctu_Ip_GetFifoResult API I see the following order

This is not as per the expectation. Could you help me with what is going wrong?

P.S.: The sample time for all the ADC's are the same.

Re: PWM_BCTU_ADC

Ayaz — Wed, 11 Dec 2024 11:45:09 GMT

The sequence must be
eMios0_Ch3->ADC0.Ch38

eMios0_Ch3->ADC0.Ch39

eMios0_Ch1->ADC1.Ch6

eMios0_Ch1->ADC1.Ch7

eMios0_Ch2->ADC2_Ch4

eMios0_Ch2->ADC2_Ch3

Re: PWM_BCTU_ADC

Senlent — Fri, 13 Dec 2024 12:05:28 GMT

Hi@Ayaz

This is probably because the interval between your emios triggering BCTU is too short, causing a timing error. You can increase the trigger interval and try again.

Re: PWM_BCTU_ADC

Samuel_DCosta — Fri, 13 Dec 2024 14:36:03 GMT

Hi,

With respect to your timing diagram, would the 'BCTU Trigger' be triggered every time the ADC is triggered by the BCTU (BCTU output trigger) or the eMIOS triggers the BCTU (BCTU input trigger)?

Also, if we have a MPC (cross trigger) where the 6 signals were triggered in the below way:
- signal 1 and signal 2 parallelly sampled
- signal 3 and signal 4 parallelly sampled
- signal 5 and signal 6 parallelly sampled
Would we still see the 'BCTU Trigger' triggered 6 times or 3?

Re: PWM_BCTU_ADC

Senlent — Sun, 15 Dec 2024 07:27:26 GMT

Hi@Samuel_DCosta

Please ignore the previous answer

1.Would the 'BCTU Trigger' be triggered every time the ADC is triggered by the BCTU (BCTU output trigger) or the eMIOS triggers the BCTU (BCTU input trigger)?

According to the BCTU MCR->TRGF register,it should be the fisrt one which is BCTU output trigger to ADC.

2.Also, if we have a MPC (cross trigger) where the 6 signals were triggered in the below way:
- signal 1 and signal 2 parallelly sampled
- signal 3 and signal 4 parallelly sampled
- signal 5 and signal 6 parallelly sampled
Would we still see the 'BCTU Trigger' triggered 6 times or 3?

This is related to your BCTU configuration. You need to give me a specific configuration so that I can answer your question.

In short, there is no problem with your project and your's understanding is right.

I modified your demo and tested it.（Please refer to the attachments）

The incorrect data order in the FIFO may be caused by the following reasons.

You will find that this is because there are some problems in the first cycle of PWM, which leads to inconsistent FIFO storage order.

I modified the trigger points of OPWMT to Ch3, Ch1, Ch2, the watermask value is 3, and the sampling is 4 times each time the trigger is triggered, for a total of 12 samples.