topic Re: STCU2 BIST ERR_STAT analyse question in S32K

STCU2 BIST ERR_STAT analyse question

rory2 — Mon, 02 Dec 2024 12:13:37 GMT

background:

chip s32k341,

SPD 1.0.4 version,

WDG->WDGEOC = 0x61A7UL.

problem description:

ST_DONE functional reset happened after running Bist_Run(BIST_SAFETYBOOT_CFG), reading ERR_STAT register shows that WDTOSW bit and RFSF bit are set.

What are the possible reasons?

thank you.

petervlna — Tue, 03 Dec 2024 08:54:43 GMT

Hello,

In other words, your watchdog timer guarding BIST execution has expired and BIST was aborted.

You can enhance timer in the STCU2 Watchdog Granularity (WDG)

RFSF is most probably set due to the WDG timeout.

Best regards,

Peter

rory2 — Wed, 04 Dec 2024 05:35:16 GMT

Hello,

I try to increase the STCU2 Watchdog Granularity (WDG) to 0x2625A00(about 16 seconds), but the result doesn't change.

The codes also meet these prerequisities:

STCU2 regs after ST_DONE functional reset are shown below.

Could there be other causes?

thank you

petervlna — Wed, 04 Dec 2024 11:48:43 GMT

Hello,

Hmm, ok. I never used SPD to run the BIST.

But you can also have following issue:

Can you play with pointer and reduce number of concurrent BIST running? Not sure which degree of configuration SPD offers.

Also, it is possible

best regards,

Peter

rory2 — Tue, 10 Dec 2024 11:09:40 GMT

I finally solved the problem, and maybe I can give you some help:

1. I chose s32k341 in EB, but there is a macro definition only s32k342, resulting in an incorrect value.

2. My project does not use QSPI and EMAC, but BIST needs to enable the clock of these peripherals.