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    <title>S32KのトピックMR-CANHUBK3 keeps resetting</title>
    <link>https://community.nxp.com/t5/S32K/MR-CANHUBK3-keeps-resetting/m-p/2005235#M43807</link>
    <description>&lt;P&gt;Hello,&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have an MR-CANHUBK3 board with an S32K344.&lt;/P&gt;&lt;P&gt;I uploaded a Zephyr code with clock settings I was testing with changes in the zephyrproject/modules/hal/nxp/s32/soc/s32k344/src/Clock_Ip_Cfg.c file:&lt;/P&gt;&lt;P&gt;&lt;EM&gt;{&lt;/EM&gt;&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;EM&gt;1U, /* clkConfigId */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(NULL_PTR), /* Register data if register value optimization is enabled */&lt;/EM&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;EM&gt;0U, /* ircoscsCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;0U, /* xoscsCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;0U, /* pllsCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;3U, /* selectorsCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;3U, /* dividersCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;0U, /* dividerTriggersCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;0U, /* fracDivsCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;2U, /* extClksCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;100U, /* gatesCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;0U, /* pcfsCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;4U, /* cmusCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;6U, /* configureFrequenciesCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;EM&gt;(&amp;amp;Clock_Ip_IrcoscConfigurations_0), /* Ircosc configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(&amp;amp;Clock_Ip_XoscConfigurations_0), /* Xosc configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(&amp;amp;Clock_Ip_PllConfigurations_0), /* Pll configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(&amp;amp;Clock_Ip_SelectorConfigurations_1), /* Selectors configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(&amp;amp;Clock_Ip_DividerConfigurations_1), /* dividers configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(NULL_PTR), /* dividerTriggers configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(NULL_PTR), /* fracDivs configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(&amp;amp;Clock_Ip_ExtClkConfigurations_1), /* extClks configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(&amp;amp;Clock_Ip_GatesConfigurations_1), /* gates configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(NULL_PTR), /* pcfs configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(&amp;amp;Clock_Ip_CmuConfigurations_1), /* cmus configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(&amp;amp;Clock_Ip_ConfiguredFrequencyConfigurations_1), /* configureFrequencies configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;},&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;After that, I cannot upload any code to the device.&amp;nbsp;&lt;/SPAN&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I also tried deleting the flashed code through J-Link and I got the following:&lt;/P&gt;&lt;P&gt;&lt;EM&gt;JLinkExe&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;SEGGER J-Link Commander V8.10f (Compiled Nov 6 2024 16:11:03)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;DLL version V8.10f, compiled Nov 6 2024 16:09:58&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;Connecting to J-Link via USB...O.K.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Firmware: J-Link V10 compiled Jan 30 2023 11:28:07&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Hardware version: V10.10&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;J-Link uptime (since boot): N/A (Not supported by this model)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;S/N: 600109715&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;License(s): RDI, FlashBP, FlashDL, JFlash, GDB&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;VTref=3.328V&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;EM&gt;Type "connect" to establish a target connection, '?' for help&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;J-Link&amp;gt;connect&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Please specify device / core. &amp;lt;Default&amp;gt;: S32K344&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Type '?' for selection dialog&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Device&amp;gt;connect S32K344&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Please specify target interface:&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;J) JTAG (Default)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;S) SWD&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;F) FINE&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;I) ICSP&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;C) C2&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;T) cJTAG&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;TIF&amp;gt;SWD&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Specify target interface speed [kHz]. &amp;lt;Default&amp;gt;: 4000 kHz&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Speed&amp;gt;4000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;The selected device "connect" is unknown to this software version.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Device "S32K344" selected.&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;EM&gt;Connecting to target via SWD&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;ConfigTargetSettings() start&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;ConfigTargetSettings() end - Took 30us&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;InitTarget() start&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;SDA_AP detected&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Unlocking device if necessary...&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Device is not locked. Proceeding without the unlock procedure.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Checking if debug access is already enabled...&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Debug access is not enabled yet. Performing enable debug access sequence...&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Debug access enabled&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Checking if HSE firmware is installed...&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;HSE firmware detected (SWAP enabled)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Checking if Cortex-M7_0 and Cortex-M7_1 are operating in lockstep mode&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Lock step mode enabled&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;InitTarget() end - Took 104ms&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Found SW-DP with ID 0x6BA02477&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;DPIDR: 0x6BA02477&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;CoreSight SoC-400 or earlier&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP map detection skipped. Manually configured AP map found.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[0]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[1]: APB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[2]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[3]: AHB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[4]: AHB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[5]: AHB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[6]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[7]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[4]: Skipped ROMBASE read. CoreBaseAddr manually set by user&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[4]: Skipped. Could not read CPUID register&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Attach to CPU failed. Executing connect under reset.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;DPIDR: 0x6BA02477&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;CoreSight SoC-400 or earlier&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP map detection skipped. Manually configured AP map found.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[0]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[1]: APB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[2]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[3]: AHB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[4]: AHB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[5]: AHB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[6]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[7]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[4]: Skipped ROMBASE read. CoreBaseAddr manually set by user&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[4]: Skipped. Could not read CPUID register&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Could not find core in Coresight setup&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;ConfigTargetSettings() start&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;ConfigTargetSettings() end - Took 40us&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;InitTarget() start&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;SDA_AP detected&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Unlocking device if necessary...&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Device is not locked. Proceeding without the unlock procedure.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Checking if debug access is already enabled...&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Debug access is not enabled yet. Performing enable debug access sequence...&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Debug access enabled&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Checking if HSE firmware is installed...&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;HSE firmware not installed&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Checking if Cortex-M7_0 and Cortex-M7_1 are operating in lockstep mode&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Lock step mode enabled&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;InitTarget() end - Took 15.1ms&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Found SW-DP with ID 0x6BA02477&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;DPIDR: 0x6BA02477&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;CoreSight SoC-400 or earlier&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP map detection skipped. Manually configured AP map found.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[0]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[1]: APB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[2]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[3]: AHB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[4]: AHB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[5]: AHB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[6]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[7]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[4]: Skipped ROMBASE read. CoreBaseAddr manually set by user&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[4]: Core found&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;****** Error: DAP error while reading AIRCR.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Error occurred: Could not connect to the target device.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;For troubleshooting steps visit:&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;A href="https://wiki.segger.com/J-Link_Troubleshooting" target="_blank" rel="noopener nofollow noreferrer"&gt;https://wiki.segger.com/J-Link_Troubleshooting&lt;/A&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;J-Link&amp;gt;10&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Unknown command. '?' for help.&lt;/EM&gt;&lt;/P&gt;&lt;BR /&gt;&lt;P&gt;I see that the board's reset light is blinking every second. I suppose the FS26 is resetting the S32K344, so that is why&amp;nbsp;I can't do anything to the board.&amp;nbsp;&lt;/P&gt;&lt;P&gt;I saw there are reset options in the hardware manual:&amp;nbsp;&lt;/P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Svetoslav_1-1733152923892.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/313548i2302B72FA1D502C4/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Svetoslav_1-1733152923892.png" alt="Svetoslav_1-1733152923892.png" /&gt;&lt;/span&gt;&lt;P&gt;But that doesn't work for me. I use a 12V power supply, I removed the pin, turned on the power supply and inserted it again and nothing.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;How can I upload a new code which fixes the clock and stops the resetting process? Are there any other potions to stop the resetting process so I can upload code?&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
    <pubDate>Mon, 02 Dec 2024 15:23:57 GMT</pubDate>
    <dc:creator>Svetoslav</dc:creator>
    <dc:date>2024-12-02T15:23:57Z</dc:date>
    <item>
      <title>MR-CANHUBK3 keeps resetting</title>
      <link>https://community.nxp.com/t5/S32K/MR-CANHUBK3-keeps-resetting/m-p/2005235#M43807</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have an MR-CANHUBK3 board with an S32K344.&lt;/P&gt;&lt;P&gt;I uploaded a Zephyr code with clock settings I was testing with changes in the zephyrproject/modules/hal/nxp/s32/soc/s32k344/src/Clock_Ip_Cfg.c file:&lt;/P&gt;&lt;P&gt;&lt;EM&gt;{&lt;/EM&gt;&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;EM&gt;1U, /* clkConfigId */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(NULL_PTR), /* Register data if register value optimization is enabled */&lt;/EM&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;EM&gt;0U, /* ircoscsCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;0U, /* xoscsCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;0U, /* pllsCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;3U, /* selectorsCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;3U, /* dividersCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;0U, /* dividerTriggersCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;0U, /* fracDivsCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;2U, /* extClksCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;100U, /* gatesCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;0U, /* pcfsCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;4U, /* cmusCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;6U, /* configureFrequenciesCount */&lt;/EM&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;EM&gt;(&amp;amp;Clock_Ip_IrcoscConfigurations_0), /* Ircosc configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(&amp;amp;Clock_Ip_XoscConfigurations_0), /* Xosc configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(&amp;amp;Clock_Ip_PllConfigurations_0), /* Pll configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(&amp;amp;Clock_Ip_SelectorConfigurations_1), /* Selectors configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(&amp;amp;Clock_Ip_DividerConfigurations_1), /* dividers configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(NULL_PTR), /* dividerTriggers configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(NULL_PTR), /* fracDivs configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(&amp;amp;Clock_Ip_ExtClkConfigurations_1), /* extClks configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(&amp;amp;Clock_Ip_GatesConfigurations_1), /* gates configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(NULL_PTR), /* pcfs configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(&amp;amp;Clock_Ip_CmuConfigurations_1), /* cmus configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;(&amp;amp;Clock_Ip_ConfiguredFrequencyConfigurations_1), /* configureFrequencies configurations */&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;EM&gt;},&lt;/EM&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;After that, I cannot upload any code to the device.&amp;nbsp;&lt;/SPAN&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I also tried deleting the flashed code through J-Link and I got the following:&lt;/P&gt;&lt;P&gt;&lt;EM&gt;JLinkExe&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;SEGGER J-Link Commander V8.10f (Compiled Nov 6 2024 16:11:03)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;DLL version V8.10f, compiled Nov 6 2024 16:09:58&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;Connecting to J-Link via USB...O.K.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Firmware: J-Link V10 compiled Jan 30 2023 11:28:07&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Hardware version: V10.10&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;J-Link uptime (since boot): N/A (Not supported by this model)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;S/N: 600109715&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;License(s): RDI, FlashBP, FlashDL, JFlash, GDB&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;VTref=3.328V&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;EM&gt;Type "connect" to establish a target connection, '?' for help&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;J-Link&amp;gt;connect&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Please specify device / core. &amp;lt;Default&amp;gt;: S32K344&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Type '?' for selection dialog&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Device&amp;gt;connect S32K344&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Please specify target interface:&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;J) JTAG (Default)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;S) SWD&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;F) FINE&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;I) ICSP&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;C) C2&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;T) cJTAG&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;TIF&amp;gt;SWD&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Specify target interface speed [kHz]. &amp;lt;Default&amp;gt;: 4000 kHz&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Speed&amp;gt;4000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;The selected device "connect" is unknown to this software version.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Device "S32K344" selected.&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;EM&gt;Connecting to target via SWD&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;ConfigTargetSettings() start&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;ConfigTargetSettings() end - Took 30us&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;InitTarget() start&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;SDA_AP detected&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Unlocking device if necessary...&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Device is not locked. Proceeding without the unlock procedure.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Checking if debug access is already enabled...&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Debug access is not enabled yet. Performing enable debug access sequence...&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Debug access enabled&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Checking if HSE firmware is installed...&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;HSE firmware detected (SWAP enabled)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Checking if Cortex-M7_0 and Cortex-M7_1 are operating in lockstep mode&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Lock step mode enabled&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;InitTarget() end - Took 104ms&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Found SW-DP with ID 0x6BA02477&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;DPIDR: 0x6BA02477&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;CoreSight SoC-400 or earlier&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP map detection skipped. Manually configured AP map found.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[0]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[1]: APB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[2]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[3]: AHB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[4]: AHB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[5]: AHB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[6]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[7]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[4]: Skipped ROMBASE read. CoreBaseAddr manually set by user&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[4]: Skipped. Could not read CPUID register&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Attach to CPU failed. Executing connect under reset.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;DPIDR: 0x6BA02477&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;CoreSight SoC-400 or earlier&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP map detection skipped. Manually configured AP map found.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[0]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[1]: APB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[2]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[3]: AHB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[4]: AHB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[5]: AHB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[6]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[7]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[4]: Skipped ROMBASE read. CoreBaseAddr manually set by user&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[4]: Skipped. Could not read CPUID register&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Could not find core in Coresight setup&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;ConfigTargetSettings() start&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;ConfigTargetSettings() end - Took 40us&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;InitTarget() start&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;SDA_AP detected&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Unlocking device if necessary...&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Device is not locked. Proceeding without the unlock procedure.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Checking if debug access is already enabled...&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Debug access is not enabled yet. Performing enable debug access sequence...&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Debug access enabled&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Checking if HSE firmware is installed...&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;HSE firmware not installed&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Checking if Cortex-M7_0 and Cortex-M7_1 are operating in lockstep mode&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Lock step mode enabled&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;InitTarget() end - Took 15.1ms&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Found SW-DP with ID 0x6BA02477&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;DPIDR: 0x6BA02477&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;CoreSight SoC-400 or earlier&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP map detection skipped. Manually configured AP map found.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[0]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[1]: APB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[2]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[3]: AHB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[4]: AHB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[5]: AHB-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[6]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[7]: MEM-AP (IDR: Not set, ADDR: 0x00000000)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[4]: Skipped ROMBASE read. CoreBaseAddr manually set by user&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;AP[4]: Core found&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;****** Error: DAP error while reading AIRCR.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Error occurred: Could not connect to the target device.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;For troubleshooting steps visit:&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;A href="https://wiki.segger.com/J-Link_Troubleshooting" target="_blank" rel="noopener nofollow noreferrer"&gt;https://wiki.segger.com/J-Link_Troubleshooting&lt;/A&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;J-Link&amp;gt;10&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Unknown command. '?' for help.&lt;/EM&gt;&lt;/P&gt;&lt;BR /&gt;&lt;P&gt;I see that the board's reset light is blinking every second. I suppose the FS26 is resetting the S32K344, so that is why&amp;nbsp;I can't do anything to the board.&amp;nbsp;&lt;/P&gt;&lt;P&gt;I saw there are reset options in the hardware manual:&amp;nbsp;&lt;/P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Svetoslav_1-1733152923892.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/313548i2302B72FA1D502C4/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Svetoslav_1-1733152923892.png" alt="Svetoslav_1-1733152923892.png" /&gt;&lt;/span&gt;&lt;P&gt;But that doesn't work for me. I use a 12V power supply, I removed the pin, turned on the power supply and inserted it again and nothing.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;How can I upload a new code which fixes the clock and stops the resetting process? Are there any other potions to stop the resetting process so I can upload code?&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Mon, 02 Dec 2024 15:23:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/MR-CANHUBK3-keeps-resetting/m-p/2005235#M43807</guid>
      <dc:creator>Svetoslav</dc:creator>
      <dc:date>2024-12-02T15:23:57Z</dc:date>
    </item>
    <item>
      <title>Re: MR-CANHUBK3 keeps resetting</title>
      <link>https://community.nxp.com/t5/S32K/MR-CANHUBK3-keeps-resetting/m-p/2007417#M43897</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I will follow up this question on your ticket&amp;nbsp;&lt;SPAN&gt;00669373&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 04 Dec 2024 20:49:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/MR-CANHUBK3-keeps-resetting/m-p/2007417#M43897</guid>
      <dc:creator>ErikaC</dc:creator>
      <dc:date>2024-12-04T20:49:45Z</dc:date>
    </item>
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