<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>S32K中的主题 回复： s32k312 spi2  clock wire ouput extra pulse at begining.</title>
    <link>https://community.nxp.com/t5/S32K/s32k312-spi2-clock-wire-ouput-extra-pulse-at-begining/m-p/2001863#M43662</link>
    <description>1. sck pull-up resistor cause this problem.&lt;BR /&gt;2. spi-sd need send data with CS high, so manually control cs instead of lpspi2_pcs0.&lt;BR /&gt;</description>
    <pubDate>Tue, 26 Nov 2024 09:44:31 GMT</pubDate>
    <dc:creator>victory</dc:creator>
    <dc:date>2024-11-26T09:44:31Z</dc:date>
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      <title>s32k312 spi2  clock wire ouput extra pulse at begining.</title>
      <link>https://community.nxp.com/t5/S32K/s32k312-spi2-clock-wire-ouput-extra-pulse-at-begining/m-p/2000441#M43572</link>
      <description>&lt;P&gt;Hi Nxp,&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; i am using s32k312 spi2 to send&amp;nbsp; data. and found spi2 clk line always output extra one pulse&amp;nbsp; as&amp;nbsp; pic below(blue waveform is clock line),&amp;nbsp; how's that happen. it not happened in spi1.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;attached is a sample project.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="victory_0-1732323536670.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/312126i11A60B46DA85B895/image-size/medium?v=v2&amp;amp;px=400" role="button" title="victory_0-1732323536670.png" alt="victory_0-1732323536670.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sat, 23 Nov 2024 01:01:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/s32k312-spi2-clock-wire-ouput-extra-pulse-at-begining/m-p/2000441#M43572</guid>
      <dc:creator>victory</dc:creator>
      <dc:date>2024-11-23T01:01:45Z</dc:date>
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    <item>
      <title>Re: s32k312 spi2  clock wire ouput extra pulse at begining.</title>
      <link>https://community.nxp.com/t5/S32K/s32k312-spi2-clock-wire-ouput-extra-pulse-at-begining/m-p/2000468#M43575</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The extra clock pulse on the SPI2 clock line is definitely interesting, especially since it doesn’t happen on SPI1. This could be caused by a configuration mismatch in SPI2 settings, such as clock polarity, phase, or transfer mode. It’s also worth checking if SPI2 handles idle states differently or if there’s a subtle difference in how the driver or SDK is managing it. Hardware issues like signal integrity could also play a role, though it’s less likely.&lt;/P&gt;</description>
      <pubDate>Sat, 23 Nov 2024 06:55:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/s32k312-spi2-clock-wire-ouput-extra-pulse-at-begining/m-p/2000468#M43575</guid>
      <dc:creator>judith75hodges</dc:creator>
      <dc:date>2024-11-23T06:55:58Z</dc:date>
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    <item>
      <title>回复： s32k312 spi2  clock wire ouput extra pulse at begining.</title>
      <link>https://community.nxp.com/t5/S32K/s32k312-spi2-clock-wire-ouput-extra-pulse-at-begining/m-p/2000524#M43589</link>
      <description>&lt;P&gt;attached files&lt;/P&gt;</description>
      <pubDate>Sun, 24 Nov 2024 00:42:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/s32k312-spi2-clock-wire-ouput-extra-pulse-at-begining/m-p/2000524#M43589</guid>
      <dc:creator>victory</dc:creator>
      <dc:date>2024-11-24T00:42:07Z</dc:date>
    </item>
    <item>
      <title>回复： s32k312 spi2  clock wire ouput extra pulse at begining.</title>
      <link>https://community.nxp.com/t5/S32K/s32k312-spi2-clock-wire-ouput-extra-pulse-at-begining/m-p/2001554#M43650</link>
      <description>&lt;P&gt;I tested your attached project and did not see the waveform mentioned in your screenshot(I don't see any SPI data at all). Please re-upload the test project.&lt;BR /&gt;In addition, why do you use PTE11 as GPIO(PCS) instead of configuring PTE11 as &lt;STRONG&gt;lpspi2_pcs0&lt;/STRONG&gt;?&lt;/P&gt;
&lt;P&gt;Also, why call IP_LPSPI_2-&amp;gt;TCR |= speed &amp;lt;&amp;lt; 27; instead of using the &lt;EM&gt;S32 Configuration Tool&lt;/EM&gt; to configure &lt;STRONG&gt;SpiBaudrate&lt;/STRONG&gt;?&lt;/P&gt;
&lt;P&gt;It is recommended to refer to the &lt;STRONG&gt;Lpspi_Flexio_Ip_Transfer_S32K344&lt;/STRONG&gt;, &lt;STRONG&gt;Lpspi_Ip_HalfDuplexTransfer_S32K344&lt;/STRONG&gt; projects in S32K3 RTD 4.0.0 or &lt;A href="https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-SPI-Transmit-amp-Receive-Using-DMA-DS3-5-RTD300/ta-p/1787856" target="_self"&gt;Example S32K312 SPI Transmit &amp;amp; Receive Using DMA DS3.5 RTD300&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 26 Nov 2024 03:37:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/s32k312-spi2-clock-wire-ouput-extra-pulse-at-begining/m-p/2001554#M43650</guid>
      <dc:creator>Robin_Shen</dc:creator>
      <dc:date>2024-11-26T03:37:37Z</dc:date>
    </item>
    <item>
      <title>回复： s32k312 spi2  clock wire ouput extra pulse at begining.</title>
      <link>https://community.nxp.com/t5/S32K/s32k312-spi2-clock-wire-ouput-extra-pulse-at-begining/m-p/2001863#M43662</link>
      <description>1. sck pull-up resistor cause this problem.&lt;BR /&gt;2. spi-sd need send data with CS high, so manually control cs instead of lpspi2_pcs0.&lt;BR /&gt;</description>
      <pubDate>Tue, 26 Nov 2024 09:44:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/s32k312-spi2-clock-wire-ouput-extra-pulse-at-begining/m-p/2001863#M43662</guid>
      <dc:creator>victory</dc:creator>
      <dc:date>2024-11-26T09:44:31Z</dc:date>
    </item>
  </channel>
</rss>

