S32K3 Flexcan FIFO MB

Jon123 — Fri, 01 Nov 2024 08:41:01 GMT

Page 38 of RTD_CAN_43_FLEXCAN_UM.pdf：

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3.6.3 Legacy Rx FIFO Configuration The receive-only FIFO is enabled for specific controller by
asserting the FEN bit in the MCR register. The Legacy RxFifo configuration in the Tresos plugin is implemented
by selection CanRxFiFo tab to CanLegacyFiFo in CanRxFiFo container.
When the Fifo is enabled, the memory region normally occupied by the first 6 MBs is normally reserved for use of
the Fifo engine. The CPU can read the received frames sequentially, in the order they were received, by repeatedly
accessing the MB0 structure.
The interrupts corresponding to MB0 to 5 have a different behavior when Rx Fifo in enabled. Bit 7 of the IFLAG1
becomes the “Fifo Overflow” flag, bit 6 becomes the “Fifo Warning” flag, bit 5 becomes the “Frame Available in Rx
Fifo” flag and bits 4 to 0 are unused. If Legacy RxFifo is enabled for a specific controller, the user shall configure at
least 1 hardware object which use that controller.

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As far as I know, when Legacy RX FIFO is activated, the RAM where the first six standard X mailboxes are located becomes six RX FIFO in depth, and then becomes a Filter table element. Combined with the diagram in the above RTD_CAN_43_FLEXCAN_UM manual and the practical application, it can be seen that only MB0 is being used, so the other five MB's functions are different in the UM manual, but I can't find the specific functions of the other five MB's, that is, M1-M5. Can you answer my doubts? Thank you.

Re: S32K3 Flexcan FIFO MB

Senlent — Mon, 04 Nov 2024 08:51:56 GMT

Hi@Jon123

This area is reserved for internal use of the Legacy RX FIFO engine,

S32KのトピックS32K3 Flexcan FIFO MB

S32K3 Flexcan FIFO MB

Re: S32K3 Flexcan FIFO MB