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    <title>topic Re: S32K358 Multicore operations between CM7_0 and CM7_2 in S32K</title>
    <link>https://community.nxp.com/t5/S32K/S32K358-Multicore-operations-between-CM7-0-and-CM7-2/m-p/1982133#M42546</link>
    <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/160001"&gt;@danielmartynek&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have reffered the IPCF burst example project and edited my S32K358 Multicore code . I have added the Platform MCAL driver and IPCF middleware driver to both M7_0_0 and M7_0_2 projects. I have made sure that i had he MCU MCAL driver in the M7_0_0 project. I have followed these driver configurations as per the example codes.&lt;/P&gt;&lt;P&gt;Once the programs are flashed, the execution gets interrupted in the IPCF hw instance initialisation. I am getting a hardfualt due to the IPCF interrupt set for core0. I am getting the exact same issue for core2.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="soumik1506_0-1729867459932.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/307028iB76A4D49DA1FA51A/image-size/medium?v=v2&amp;amp;px=400" role="button" title="soumik1506_0-1729867459932.png" alt="soumik1506_0-1729867459932.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;When i simply ran the IPCF example given in the examples library, i am getting hard fault error for a different reason. On analysing it, i found out it is something to do queue write and read sizes with the managed/un-managed channels configured for IPCF instances.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="soumik1506_1-1729867738290.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/307029iCF6F474F220C3C8A/image-size/medium?v=v2&amp;amp;px=400" role="button" title="soumik1506_1-1729867738290.png" alt="soumik1506_1-1729867738290.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Just be clear, i have not made any configurations with respect to the IPCF example and the multicore code. Please find the attached projects and please tell me where and what am i missing.&lt;/P&gt;&lt;P&gt;Is there any reference or a user manual that i can go through, and helps me understand the ins-and-outs of the IPCF middleware driver.&lt;/P&gt;&lt;P&gt;Soumik&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Fri, 25 Oct 2024 14:59:46 GMT</pubDate>
    <dc:creator>soumik1506</dc:creator>
    <dc:date>2024-10-25T14:59:46Z</dc:date>
    <item>
      <title>S32K358 Multicore operations between CM7_0 and CM7_2</title>
      <link>https://community.nxp.com/t5/S32K/S32K358-Multicore-operations-between-CM7-0-and-CM7-2/m-p/1981377#M42495</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/160001"&gt;@danielmartynek&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;i am currently working on a project that requires the core 0 and core 2 of the S32K358 board to perform operations and pass data both ways.&lt;/P&gt;&lt;P&gt;i have come across your &lt;A href="https://community.nxp.com/t5/S32K-Knowledge-Base/S32K358-Multicore-Start-CM7-2-from-CM7-0/ta-p/1923889" target="_blank" rel="noopener"&gt;article&lt;/A&gt; that demos the how to power the core 2 and control the leds on the board. Is there a way i can send the state of the led in Core 2 to Core 0. If so, what do i have to do.&lt;/P&gt;</description>
      <pubDate>Thu, 24 Oct 2024 15:34:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K358-Multicore-operations-between-CM7-0-and-CM7-2/m-p/1981377#M42495</guid>
      <dc:creator>soumik1506</dc:creator>
      <dc:date>2024-10-24T15:34:10Z</dc:date>
    </item>
    <item>
      <title>Re: S32K358 Multicore operations between CM7_0 and CM7_2</title>
      <link>https://community.nxp.com/t5/S32K/S32K358-Multicore-operations-between-CM7-0-and-CM7-2/m-p/1981782#M42522</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/240794"&gt;@soumik1506&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Use &lt;STRONG&gt;Inter-Platform Communication Framework (IPCF)&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/design/design-center/software/automotive-software-and-tools/inter-platform-communication-framework-ipcf:IPCF" target="_blank"&gt;https://www.nxp.com/design/design-center/software/automotive-software-and-tools/inter-platform-communication-framework-ipcf:IPCF&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Which is an extension to the RTD and it is available in the S32K3 Standard Software.&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/webapp/swlicensing/sso/downloadSoftware.sp?catid=SW32K3-STDSW-D" target="_blank"&gt;https://www.nxp.com/webapp/swlicensing/sso/downloadSoftware.sp?catid=SW32K3-STDSW-D&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Please read the release notes of the SW, it specifies compatible RTD versions.&lt;/P&gt;
&lt;P&gt;Once it is installed in S32DS IDE, create a project from example:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="danielmartynek_0-1729839387549.png" style="width: 594px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/306931iD744A7F697944827/image-dimensions/594x411?v=v2" width="594" height="411" role="button" title="danielmartynek_0-1729839387549.png" alt="danielmartynek_0-1729839387549.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Daniel&lt;/P&gt;</description>
      <pubDate>Fri, 25 Oct 2024 06:57:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K358-Multicore-operations-between-CM7-0-and-CM7-2/m-p/1981782#M42522</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2024-10-25T06:57:48Z</dc:date>
    </item>
    <item>
      <title>Re: S32K358 Multicore operations between CM7_0 and CM7_2</title>
      <link>https://community.nxp.com/t5/S32K/S32K358-Multicore-operations-between-CM7-0-and-CM7-2/m-p/1982133#M42546</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/160001"&gt;@danielmartynek&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have reffered the IPCF burst example project and edited my S32K358 Multicore code . I have added the Platform MCAL driver and IPCF middleware driver to both M7_0_0 and M7_0_2 projects. I have made sure that i had he MCU MCAL driver in the M7_0_0 project. I have followed these driver configurations as per the example codes.&lt;/P&gt;&lt;P&gt;Once the programs are flashed, the execution gets interrupted in the IPCF hw instance initialisation. I am getting a hardfualt due to the IPCF interrupt set for core0. I am getting the exact same issue for core2.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="soumik1506_0-1729867459932.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/307028iB76A4D49DA1FA51A/image-size/medium?v=v2&amp;amp;px=400" role="button" title="soumik1506_0-1729867459932.png" alt="soumik1506_0-1729867459932.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;When i simply ran the IPCF example given in the examples library, i am getting hard fault error for a different reason. On analysing it, i found out it is something to do queue write and read sizes with the managed/un-managed channels configured for IPCF instances.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="soumik1506_1-1729867738290.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/307029iCF6F474F220C3C8A/image-size/medium?v=v2&amp;amp;px=400" role="button" title="soumik1506_1-1729867738290.png" alt="soumik1506_1-1729867738290.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Just be clear, i have not made any configurations with respect to the IPCF example and the multicore code. Please find the attached projects and please tell me where and what am i missing.&lt;/P&gt;&lt;P&gt;Is there any reference or a user manual that i can go through, and helps me understand the ins-and-outs of the IPCF middleware driver.&lt;/P&gt;&lt;P&gt;Soumik&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 25 Oct 2024 14:59:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K358-Multicore-operations-between-CM7-0-and-CM7-2/m-p/1982133#M42546</guid>
      <dc:creator>soumik1506</dc:creator>
      <dc:date>2024-10-25T14:59:46Z</dc:date>
    </item>
    <item>
      <title>Re: S32K358 Multicore operations between CM7_0 and CM7_2</title>
      <link>https://community.nxp.com/t5/S32K/S32K358-Multicore-operations-between-CM7-0-and-CM7-2/m-p/2055682#M46451</link>
      <description>&lt;P&gt;What was the solution for the IPCF Example SW issue? I am running into the same challenges.&lt;/P&gt;</description>
      <pubDate>Tue, 04 Mar 2025 17:22:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K358-Multicore-operations-between-CM7-0-and-CM7-2/m-p/2055682#M46451</guid>
      <dc:creator>Dave_PE</dc:creator>
      <dc:date>2025-03-04T17:22:35Z</dc:date>
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