topic Re: UJA1167 WATCHDOG in S32K

UJA1167 WATCHDOG

PINKMAN — Wed, 23 Oct 2024 07:59:12 GMT

hello,expert:

there is strange that when i set the UJA1167 watchdog period as 8ms,and i test the reset pin i found the reset time is 19ms.when i set period as 64ms，the reset time is 128ms？it is weird!!!

Reset time is about twice as long as the timeout time

Re: UJA1167 WATCHDOG

JozefKozon — Thu, 24 Oct 2024 05:43:25 GMT

Hello Pinkman,

this is indeed a strange behavior. Could you please share a scope of the SPI pins when you are writing to the Watchdog control register? Please confirm what watchdog mode you are setting. Are you able to set the watchdog period to the 4096ms? NWP to 0111?

The waveform you shared comes from the RSTN pin, right?

Please share the Main status register (address 03h), Watchdog status register (address 05h) and System event status register (address 61h) content before and after reset.

With Best Regards,

Jozef

Re: UJA1167 WATCHDOG

PINKMAN — Wed, 06 Nov 2024 05:46:29 GMT

This reset cycle is indeed twice as long as the timer, as I found the following information in the reference manual, can you help me to confirm if my understanding is correct.

My understanding is that in timeout mode, the first overflow generates a WDF, and only the second overflow generates a reset. This explains why I set the timeout to 64ms and the reset to around 128ms!

Re: UJA1167 WATCHDOG

JozefKozon — Thu, 07 Nov 2024 06:22:49 GMT

Hello Pinkman,

thank you very much for your research. Yes, it makes sense. The Watchdog overflow must happened twice. This is also confirmed in the Table 5. in the UJA1167 datasheet. The first watchdog overflow is detected and the WDF bit is set to 1. Then with the second Watchdog overflow the reset is conducted. This confirms your conclusion. Thank you for pointing me to that.

With Best Regards,

Jozef