Flexcan test issues on FPGA board

karsen — Fri, 18 Oct 2024 02:22:58 GMT

Hi dears:

I have met some flexcan issues on my FPAG board

test enviroment : FPGA core frequency is 32M， flexcan peripheral clock and oscillator clock are both collect to 40M， the software is contiously send canfd frames:

1. when I configure a baudrate with 500K + 2M， there is no problem

2. when I configure a baudrate with 1M + 2M， there are some "unexpected can frames" occured on the bus (I use logic analyzer to watch them),

2.1 the canfd frames is send out as expected

2.2 the can frame is immediately(11 bits) followed by the canfd frame

2.3 flexcan will report bit error when send these can frames

3. when I configure a baudrate with 500K + 4M/5M, the TDC is on, and TDC offset is 3

there is only one frame send out, and there is no error report , I have watch the MB SRAM, the MB cs code is always "TX DATA," no update .

wish to hear from you, thanks !

Re: Flexcan test issues on FPGA board

PetrS — Mon, 21 Oct 2024 11:33:15 GMT

Hi,

which devices are used in fact? You have some FPGA connected to S32K device, or what?
It would be great you share screenshots for unexpected can frames and errors detected.
A behavior can indicate inconsistent CAN bit timing used on CAN bus. Be sure all nodes connected use a same bit timing.
For 40MHz PE clock and 4Mbps set TDC offset higher, i.e. 6-8.

BR, Petr

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Flexcan test issues on FPGA board

Re: Flexcan test issues on FPGA board