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  <channel>
    <title>topic Re: What is S32K3 PLL Loss of Lock? in S32K</title>
    <link>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1968454#M41738</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;PLL LOL is permanently turned on. It is one of the&amp;nbsp;Destructive reset sources (please refer to chapter 31.3.3 in RM_rev9).&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Pavel&lt;/P&gt;</description>
    <pubDate>Tue, 08 Oct 2024 05:36:50 GMT</pubDate>
    <dc:creator>PavelL</dc:creator>
    <dc:date>2024-10-08T05:36:50Z</dc:date>
    <item>
      <title>What is S32K3 PLL Loss of Lock?</title>
      <link>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1967429#M41657</link>
      <description>&lt;P&gt;Hi NXP,&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;&amp;nbsp;&lt;SPAN&gt;I am looking at the PLL Loss of Lock in the S32K3 chip manual, please answer my questions below.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; 1.&lt;SPAN&gt;What is PLL Loss of Lock?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp;2.What do the formulas in the manual mean?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="li3_0-1728209722708.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/302921i51CC5B28D375C5FA/image-size/medium?v=v2&amp;amp;px=400" role="button" title="li3_0-1728209722708.png" alt="li3_0-1728209722708.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Best regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Li 3.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Sun, 06 Oct 2024 10:16:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1967429#M41657</guid>
      <dc:creator>li3</dc:creator>
      <dc:date>2024-10-06T10:16:58Z</dc:date>
    </item>
    <item>
      <title>Re: What is S32K3 PLL Loss of Lock?</title>
      <link>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1967700#M41677</link>
      <description>&lt;P&gt;Hi Li 3,&lt;/P&gt;
&lt;P&gt;since PLL is a general, common used block, please refer to PLL general description&amp;nbsp;&lt;A href="https://en.wikipedia.org/wiki/Phase-locked_loop" target="_blank"&gt;Phase-locked loop - Wikipedia.&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;1. PLL Loss of lock means big failure of PLL - output frequency goes over acceptable limits.&lt;/P&gt;
&lt;P&gt;2. The formulas show how is PLL's output frequency calculated during different modes.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Pavel&lt;/P&gt;</description>
      <pubDate>Mon, 07 Oct 2024 07:39:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1967700#M41677</guid>
      <dc:creator>PavelL</dc:creator>
      <dc:date>2024-10-07T07:39:49Z</dc:date>
    </item>
    <item>
      <title>Re: What is S32K3 PLL Loss of Lock?</title>
      <link>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1967720#M41679</link>
      <description>Hi NXP，&lt;BR /&gt;Think you for your reply.&lt;BR /&gt;1.How to configure PLL LOL in S32DS software?&lt;BR /&gt;2.How does LOL automatically monitor the PLL clock?&lt;BR /&gt;&lt;BR /&gt;Best regards,&lt;BR /&gt;Li 3.</description>
      <pubDate>Mon, 07 Oct 2024 08:10:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1967720#M41679</guid>
      <dc:creator>li3</dc:creator>
      <dc:date>2024-10-07T08:10:44Z</dc:date>
    </item>
    <item>
      <title>Re: What is S32K3 PLL Loss of Lock?</title>
      <link>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1967910#M41694</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;PLL LOL is not configurable. There is only configurable lock counter - please refer to RM_rev9 30.6.7 PLL Calibration Register 2 (PLLCAL2) for details.&lt;/P&gt;
&lt;P&gt;LOL monitor is a part of PLL IP, so there are no more details to be shared.&lt;/P&gt;
&lt;P&gt;As it is written in RM:&amp;nbsp;PLL LOL is intended for detection of gross failures. Use CMUs for accurate frequency monitoring.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Pavel&lt;/P&gt;</description>
      <pubDate>Mon, 07 Oct 2024 13:35:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1967910#M41694</guid>
      <dc:creator>PavelL</dc:creator>
      <dc:date>2024-10-07T13:35:40Z</dc:date>
    </item>
    <item>
      <title>Re: What is S32K3 PLL Loss of Lock?</title>
      <link>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1967914#M41696</link>
      <description>Hi，&lt;BR /&gt;Think you for your reply.&lt;BR /&gt;How to enable PLL LOL?&lt;BR /&gt;Best regards,&lt;BR /&gt;Li 3.</description>
      <pubDate>Mon, 07 Oct 2024 13:43:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1967914#M41696</guid>
      <dc:creator>li3</dc:creator>
      <dc:date>2024-10-07T13:43:00Z</dc:date>
    </item>
    <item>
      <title>Re: What is S32K3 PLL Loss of Lock?</title>
      <link>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1968454#M41738</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;PLL LOL is permanently turned on. It is one of the&amp;nbsp;Destructive reset sources (please refer to chapter 31.3.3 in RM_rev9).&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Pavel&lt;/P&gt;</description>
      <pubDate>Tue, 08 Oct 2024 05:36:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1968454#M41738</guid>
      <dc:creator>PavelL</dc:creator>
      <dc:date>2024-10-08T05:36:50Z</dc:date>
    </item>
    <item>
      <title>Re: What is S32K3 PLL Loss of Lock?</title>
      <link>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1968594#M41752</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Hi&amp;nbsp;NXP，&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;PLL LOL Destructive reset Demoted to interrupt Can only write program configuration registers?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="li3_0-1728369761799.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/303313i3697B08F4107B857/image-size/medium?v=v2&amp;amp;px=400" role="button" title="li3_0-1728369761799.png" alt="li3_0-1728369761799.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Best regards,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Li 3.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 08 Oct 2024 06:44:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1968594#M41752</guid>
      <dc:creator>li3</dc:creator>
      <dc:date>2024-10-08T06:44:16Z</dc:date>
    </item>
    <item>
      <title>Re: What is S32K3 PLL Loss of Lock?</title>
      <link>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1968639#M41755</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;yes, set field&amp;nbsp;DEST_RST9_AS_IPI to 1 (of register DCMRWP3) to configure a destructive reset to interrupt.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Pavel&lt;/P&gt;</description>
      <pubDate>Tue, 08 Oct 2024 07:19:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1968639#M41755</guid>
      <dc:creator>PavelL</dc:creator>
      <dc:date>2024-10-08T07:19:31Z</dc:date>
    </item>
    <item>
      <title>Re: What is S32K3 PLL Loss of Lock?</title>
      <link>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1968763#M41767</link>
      <description>&lt;P&gt;Hi&amp;nbsp;NXP，&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The DCMRWF2.PLL1_LOL_RST _EN bit is used to set the LOL destructive restart or interrupt. What is the relationship between this bit and the DCMRWP3.DEST_RST9_A S_IPI bit?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="li3_0-1728377790268.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/303364iA9547D704FC567C5/image-size/medium?v=v2&amp;amp;px=400" role="button" title="li3_0-1728377790268.png" alt="li3_0-1728377790268.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Best regards,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Li 3.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 08 Oct 2024 08:59:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1968763#M41767</guid>
      <dc:creator>li3</dc:creator>
      <dc:date>2024-10-08T08:59:30Z</dc:date>
    </item>
    <item>
      <title>Re: What is S32K3 PLL Loss of Lock?</title>
      <link>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1968862#M41772</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;DCMRWF2 is related to the Functional reset (this is not available for all members of S32K3 family),&amp;nbsp;DCMRWP3 is related to the destructive reset. Please refer to Chapter 31 and 33 in RM_rev9 for details about reset.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Pavel&lt;/P&gt;</description>
      <pubDate>Tue, 08 Oct 2024 11:21:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1968862#M41772</guid>
      <dc:creator>PavelL</dc:creator>
      <dc:date>2024-10-08T11:21:24Z</dc:date>
    </item>
    <item>
      <title>Re: What is S32K3 PLL Loss of Lock?</title>
      <link>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1968978#M41783</link>
      <description>&lt;P&gt;Hi&amp;nbsp;NXP，&lt;/P&gt;&lt;P&gt;1.&lt;SPAN&gt;According to the manual, LOL can only be used in PLL functional mode, so PLL is configured to automatically open LOL in functional mode.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="li3_1-1728395784520.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/303427i96E6460193C97446/image-size/medium?v=v2&amp;amp;px=400" role="button" title="li3_1-1728395784520.png" alt="li3_1-1728395784520.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="li3_2-1728395934227.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/303428i468E4F2DA6708A70/image-size/medium?v=v2&amp;amp;px=400" role="button" title="li3_2-1728395934227.png" alt="li3_2-1728395934227.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Best regards, &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Li 3.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 08 Oct 2024 14:00:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1968978#M41783</guid>
      <dc:creator>li3</dc:creator>
      <dc:date>2024-10-08T14:00:19Z</dc:date>
    </item>
    <item>
      <title>Re: What is S32K3 PLL Loss of Lock?</title>
      <link>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1969605#M41832</link>
      <description>Hello. Is that what I said?</description>
      <pubDate>Wed, 09 Oct 2024 06:49:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1969605#M41832</guid>
      <dc:creator>li3</dc:creator>
      <dc:date>2024-10-09T06:49:00Z</dc:date>
    </item>
    <item>
      <title>Re: What is S32K3 PLL Loss of Lock?</title>
      <link>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1971018#M41881</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;yes.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Pavel&lt;/P&gt;</description>
      <pubDate>Thu, 10 Oct 2024 06:26:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/What-is-S32K3-PLL-Loss-of-Lock/m-p/1971018#M41881</guid>
      <dc:creator>PavelL</dc:creator>
      <dc:date>2024-10-10T06:26:48Z</dc:date>
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