S32K中的主题 S32K322_Pwm _Issue

S32K322_Pwm _Issue

gadilinga — Fri, 06 Sep 2024 13:24:37 GMT

Hi ,

Currently I'm Working On S32K322 Micro EMIOS Pwm But It's Not getting Any Signle From Pwm and I Configured Port Pin Level Also Its Getting Continues Low, When I select the Emios_0_CH[0]_X_OUT. another Thing I Was worked On S32K344 Board Its Working. But In S32K322 Board Its not Working so That Port Pin Mode Made As GPIO That Time Its Toggling. SO In Another Case we Are using Core_Clk for Emios Pwm As Mention In S32Kxx Reference Manual Same Thing i Did In S32K344 Its Working But In s32K322 I was Not Working So Again I used Another Clock FXOSC_Clk For Pwm Mcu Clock Reference also not working So what was issue for this. thank u

Re: S32K322_Pwm _Issue

VaneB — Fri, 06 Sep 2024 18:44:03 GMT

Hi @gadilinga

As shown in the S32K3xx Reference Manual, the only clock source of eMIOS is CORE_CLK and the clock limitations of S32K322 are the same as S32K344. So there should not be a problem with the clock configuration.

Did you configure PLL as the clock source? If so, could you check if the crystal connected to EXTAL and XTAL pins is generating the expected clock signal (I am assuming the board with the S32K322 is a custom board)?

Could you share images of the configurations made for the PWM and MCL driver configurations to check if there is no problem regarding these?

BR, VaneB

Re: S32K322_Pwm _Issue

gadilinga — Tue, 10 Sep 2024 07:21:01 GMT

Hi @VaneB ,

thank u For Ur Quick response, Yeah As u Assumed correct only we are using S32K322 Customized Board. we Check With External Clk(FXOSC_CLK_40Mhz). And PLL also We Configured. When PLL is not Working it will take Internal FIRC CLk . so Its not getting Pin High. Whatever I shared Here I Configured Its Working In S32K344 But Its Not working In S32k322 board I didn't get Root cause of this Issue.

Re: S32K322_Pwm _Issue

VaneB — Tue, 10 Sep 2024 17:31:35 GMT

Hi @gadilinga

According to the shared images the configurations seem correct, please try from the beginning setting the internal clock (FIRC) as clock source, this is to check if the problem can be caused by the external clock.

I want to check if it is not a hardware problem since the configurations and code work with the S32K344.

Re: S32K322_Pwm _Issue

gadilinga — Wed, 11 Sep 2024 05:42:41 GMT

Hi @VaneB,
Currently We Used Customize Board Was Verified By Nxp Any DifferenceIs there For Eval Board and Customize Board.

Re: S32K322_Pwm _Issue

gadilinga — Wed, 11 Sep 2024 06:39:44 GMT

Hi @VaneB,

Plz guide Us For This Issue I didn't get What was the Root Cause

Re: S32K322_Pwm _Issue

gadilinga — Wed, 11 Sep 2024 09:07:33 GMT

Hi @VaneB ,

Currently Issue Was Resolved, I got Root Cause was Allow Debug Mode when it Make True It was Not Working When I Make it False It was Working. So can I U Give me More Clarity On this. Thank u

Re: S32K322_Pwm _Issue

VaneB — Wed, 11 Sep 2024 21:40:17 GMT

Hi @gadilinga

This parameter Enables/Disables outputs to continue operation in Debug.

Re: S32K322_Pwm _Issue

gadilinga — Thu, 12 Sep 2024 04:36:03 GMT

Hi @VaneB,
Yeah! In S32K344 its Enable/Disable But It Working. In S32K322 if Its Enable Pwm output was Not Coming If Its Disable Its working. Another Thing Was Pin getting Low When Enable Debug Mode. So what is Relation B\W if We Allow the Debug Mode In s32K322. Could U Plz Guide US.

Re: S32K322_Pwm _Issue

VaneB — Thu, 12 Sep 2024 16:50:12 GMT

Hi @gadilinga

Could you help me verify that when enabling or disabling the Allow Debug Mode parameter, the code changes are observed?

Re: S32K322_Pwm _Issue

gadilinga — Fri, 13 Sep 2024 04:34:33 GMT

Hi @VaneB ,

If I enable the Allow the debug Mode it will Get set Overflow Bit.

This Is what I Seen in RM.