S32K ECC error

sherifomar — Wed, 16 Jan 2019 13:51:54 GMT

Hello,

I am using S32K118 EVB. According to the safety manual, reading flash memory can detect the double-bit uncorrectable error.

My question: is there a way to cause a double-bit uncorrectable error in the flash memory via SW?

Thank you for your support.

Regards,

Sherif

Re: S32K ECC error

danielmartynek — Wed, 16 Jan 2019 14:54:35 GMT

Hello Sherif,

Yes, it can be done by two subsequent writes (program phrase command) with different data at one flash address (phrase). Normally, the phrase must be erased before the second write. The ECC error then depends on the resulting phrase value and ECC checksum value. Then, if you read the address, ECC error will be reported.

Regards,

Daniel

Re: S32K ECC error

hajianik — Sun, 20 Feb 2022 19:21:51 GMT

Hi Daniel,

I followed your advice and yet I observe FTFC_FERSTAT remains 0 after the read to location.

The function below writes 8 bytes to location 0X0D2660 (0XAA,0X55,,,) which is 64bit aligned and then it erases it and writes 0x14,0x13,0x12......

then I read the location 0x0d2660 and look at the register I mentioned above and it still is 0x00

This function flsh_ecc run out of RAM from 0x1FFE0000 which is at top of the ram also the debugger shows me the 1st phrase is written and then erased and rewritten with a new phrase.

then I read the location:

myvar = *((unsigned long long*)0xd2660);

the only thing which is notable is :the code hangs up up and won't run anymore.

void flsh_ecc(void)
{
//while((FTFC->FSTAT & FTFC_FSTAT_CCIF_MASK) != FTFC_FSTAT_CCIF_MASK); /* Wait until any ongoing flash operation is completed */
#pragma asm
;ldr r1, =0x40020000 (0x1fff027c <run_ocs_volt_once..C.3A.5CFramework_ZERV_v00.2E02.5CApplications.5CZERV_Framework.5CAppl.5Cobj.5CINF_CDD.>)
movw r1,0x0000
movt r1,0x4002
movs r0, #128 ; 0x80
strb r0, [r1, #0]
L1:
ldrb r0, [r1, #0]
lsls r0, r0, #24
bpl L1
#pragma endasm
//FTFC->FSTAT = FTFC_FSTAT_ACCERR_MASK | FTFC_FSTAT_FPVIOL_MASK;

FTFC->FCCOB[3] = 0x07;//a_cmd; //Program Phrase command (0x07)
FTFC->FCCOB[2] = 0x0d;//v_AddrVec[0]; //Flash address [23:16]
FTFC->FCCOB[1] =0x26; //v_AddrVec[1]; //Flash address [15:08]
FTFC->FCCOB[0] =0x60; //v_AddrVec[2]; //Flash address [7:0]

// if (a_pageBuffer != NULL) {
FTFC->FCCOB[7] =0x55; //a_pageBuffer[0]; //data
FTFC->FCCOB[6] = 0xaa;//a_pageBuffer[1];
FTFC->FCCOB[5] = 0x55;//a_pageBuffer[2];
FTFC->FCCOB[4] =0xaa; //a_pageBuffer[3];
FTFC->FCCOB[11] =0x55; //a_pageBuffer[4];
FTFC->FCCOB[10] =0xaa; //a_pageBuffer[5];
FTFC->FCCOB[9] =0x55; //a_pageBuffer[6];
FTFC->FCCOB[8] =0xaa; //a_pageBuffer[7];
// }

FTFC->FSTAT = FTFC_FSTAT_CCIF_MASK; //launch command
//while((FTFC->FSTAT & FTFC_FSTAT_CCIF_MASK) != FTFC_FSTAT_CCIF_MASK);
#pragma asm
;ldr r1, =0x40020000 (0x1fff027c <run_ocs_volt_once..C.3A.5CFramework_ZERV_v00.2E02.5CApplications.5CZERV_Framework.5CAppl.5Cobj.5CINF_CDD.>)
movw r1,0x0000
movt r1,0x4002
movs r0, #128 ; 0x80
strb r0, [r1, #0]
L2:
ldrb r0, [r1, #0]
lsls r0, r0, #24
bpl L2
#pragma endasm

FTFC->FCCOB[3] = 0x09;//a_cmd; //Program Phrase command (0x07)
FTFC->FCCOB[2] = 0x0d;//v_AddrVec[0]; //Flash address [23:16]
FTFC->FCCOB[1] =0x26; //v_AddrVec[1]; //Flash address [15:08]
FTFC->FCCOB[0] =0x60; //v_AddrVec[2]; //Flash address [7:0]
FTFC->FSTAT = FTFC_FSTAT_CCIF_MASK; //launch command
#pragma asm
;ldr r1, =0x40020000 (0x1fff027c <run_ocs_volt_once..C.3A.5CFramework_ZERV_v00.2E02.5CApplications.5CZERV_Framework.5CAppl.5Cobj.5CINF_CDD.>)
movw r1,0x0000
movt r1,0x4002
movs r0, #128 ; 0x80
strb r0, [r1, #0]
L3:
ldrb r0, [r1, #0]
lsls r0, r0, #24
bpl L3
#pragma endasm
FTFC->FCCOB[3] = 0x07;//a_cmd; //Program Phrase command (0x07)
FTFC->FCCOB[2] = 0x0d;//v_AddrVec[0]; //Flash address [23:16]
FTFC->FCCOB[1] =0x26; //v_AddrVec[1]; //Flash address [15:08]
FTFC->FCCOB[0] =0x60; //v_AddrVec[2]; //Flash address [7:0]

// if (a_pageBuffer != NULL) {
FTFC->FCCOB[7] =0x10; //a_pageBuffer[0]; //data
FTFC->FCCOB[6] = 0x12;//a_pageBuffer[1];
FTFC->FCCOB[5] = 0x13;//a_pageBuffer[2];
FTFC->FCCOB[4] =0x14; //a_pageBuffer[3];
FTFC->FCCOB[11] =0x15; //a_pageBuffer[4];
FTFC->FCCOB[10] =0x16; //a_pageBuffer[5];
FTFC->FCCOB[9] =0x17; //a_pageBuffer[6];
FTFC->FCCOB[8] =0x18; //a_pageBuffer[7];
//INT_SYS_EnableIRQGlobal();
FTFC->FSTAT = FTFC_FSTAT_CCIF_MASK; //launch command
#pragma asm
;ldr r1, =0x40020000 (0x1fff027c <run_ocs_volt_once..C.3A.5CFramework_ZERV_v00.2E02.5CApplications.5CZERV_Framework.5CAppl.5Cobj.5CINF_CDD.>)
movw r1,0x0000
movt r1,0x4002
movs r0, #128 ; 0x80
strb r0, [r1, #0]
L4:
ldrb r0, [r1, #0]
lsls r0, r0, #24
bpl L4
#pragma endasm

}

Just wondering beside the register FTFC-FEPRT is it some else th check.

BR,

kOOROSH

Re: S32K ECC error

hajianik — Mon, 21 Feb 2022 18:01:32 GMT

Re: S32K ECC error

hajianik — Mon, 21 Feb 2022 18:05:54 GMT

Hi Daniel,

I guess it hits the Memory fault exception when It hangs up.

There is no reset causing mechanism for this exception handler. I did not write the code for it. it is all in assembly and good luck deciphering it.

Thanks,

Re: S32K ECC error

hajianik — Mon, 21 Feb 2022 20:50:12 GMT

in my last post ,I mistakenly said it is the memory fault where actually it is "BUSFAULT" exception.

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