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    <title>topic DMA write to ADC SC1 in S32K</title>
    <link>https://community.nxp.com/t5/S32K/DMA-write-to-ADC-SC1/m-p/1935440#M39812</link>
    <description>&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;We have &amp;gt; 8 ADC inputs that I want to sample, synchronized with FTM PWM INIT trigger.&lt;/P&gt;&lt;P&gt;We're using the PDB for this. But since we have a non-W S32K, I can't use back-to-back linking of CH0 and CH1 in the PDB.&lt;/P&gt;&lt;P&gt;I figured a solution would work where the DMA (triggered by ADC COCO) will rewrite ADC_SC1n in order to "link" more inputs, pulse-by-pulse. However it seems like writing to SC1n via DMA causes the PDB to be unable to trigger the ADC again (ES for the first channel becomes high).&lt;/P&gt;&lt;P&gt;Can anyone advice on how to achieve this?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Joey&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Mon, 19 Aug 2024 15:24:55 GMT</pubDate>
    <dc:creator>Joey_van_Hummel</dc:creator>
    <dc:date>2024-08-19T15:24:55Z</dc:date>
    <item>
      <title>DMA write to ADC SC1</title>
      <link>https://community.nxp.com/t5/S32K/DMA-write-to-ADC-SC1/m-p/1935440#M39812</link>
      <description>&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;We have &amp;gt; 8 ADC inputs that I want to sample, synchronized with FTM PWM INIT trigger.&lt;/P&gt;&lt;P&gt;We're using the PDB for this. But since we have a non-W S32K, I can't use back-to-back linking of CH0 and CH1 in the PDB.&lt;/P&gt;&lt;P&gt;I figured a solution would work where the DMA (triggered by ADC COCO) will rewrite ADC_SC1n in order to "link" more inputs, pulse-by-pulse. However it seems like writing to SC1n via DMA causes the PDB to be unable to trigger the ADC again (ES for the first channel becomes high).&lt;/P&gt;&lt;P&gt;Can anyone advice on how to achieve this?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Joey&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 19 Aug 2024 15:24:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/DMA-write-to-ADC-SC1/m-p/1935440#M39812</guid>
      <dc:creator>Joey_van_Hummel</dc:creator>
      <dc:date>2024-08-19T15:24:55Z</dc:date>
    </item>
    <item>
      <title>Re: DMA write to ADC SC1</title>
      <link>https://community.nxp.com/t5/S32K/DMA-write-to-ADC-SC1/m-p/1935985#M39842</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/153543"&gt;@Joey_van_Hummel&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Which S32K1xx part do you use?&lt;/P&gt;
&lt;P&gt;CHIPCTL[PDB_BB_SEL] is supported not only on S32K14xW but S32K14x too.&lt;/P&gt;
&lt;P&gt;The S32K14x parts allow chaining PDB0_Ch0 and PDB1_Ch0 back-to-back.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="danielmartynek_0-1724140284262.png" style="width: 626px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/294064i110ADAB7F29633AC/image-dimensions/626x421?v=v2" width="626" height="421" role="button" title="danielmartynek_0-1724140284262.png" alt="danielmartynek_0-1724140284262.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Daniel&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 20 Aug 2024 07:52:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/DMA-write-to-ADC-SC1/m-p/1935985#M39842</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2024-08-20T07:52:38Z</dc:date>
    </item>
    <item>
      <title>Re: DMA write to ADC SC1</title>
      <link>https://community.nxp.com/t5/S32K/DMA-write-to-ADC-SC1/m-p/1936062#M39843</link>
      <description>&lt;P&gt;Hi Daniel,&lt;/P&gt;&lt;P&gt;Thanks for your reply. We are using an S32K142. Sadly the hardware is already definitive, and due to an oversight we have up to 11 channels on ADC0. Thus I would have liked to chain PDB0_CH0 and PDB0_CH1, but this requires PDB_BB_SEL[1] which is not available to us.&lt;/P&gt;&lt;P&gt;I was hoping to work around this by having the ADC trigger the DMA, which copies the results and then rewrites ADC-SC1n. The idea is that on the next INIT-trigger from the FTM, the remaining inputs are sampled.&lt;/P&gt;&lt;P&gt;Can you tell me if this should theoretically work? It seems like the PDB refuses to trigger ADC after writes to ADC-&amp;gt;SC1 have occurred by the DMA. So I am doubting my strategy.&lt;/P&gt;&lt;P&gt;Kind regards,&lt;/P&gt;&lt;P&gt;Joey&lt;/P&gt;</description>
      <pubDate>Tue, 20 Aug 2024 08:38:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/DMA-write-to-ADC-SC1/m-p/1936062#M39843</guid>
      <dc:creator>Joey_van_Hummel</dc:creator>
      <dc:date>2024-08-20T08:38:35Z</dc:date>
    </item>
    <item>
      <title>Re: DMA write to ADC SC1</title>
      <link>https://community.nxp.com/t5/S32K/DMA-write-to-ADC-SC1/m-p/1936286#M39852</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/153543"&gt;@Joey_van_Hummel&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;I haven't testing it, but it should work.&lt;/P&gt;
&lt;P&gt;Do you see any PDB error flags?&lt;/P&gt;
&lt;P&gt;Can you check all the PDB and ADC registers after the DMA transfer?&lt;/P&gt;
&lt;P&gt;Is there a chance you accidentally overwrite other ADC registers?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Daniel&lt;/P&gt;</description>
      <pubDate>Tue, 20 Aug 2024 12:43:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/DMA-write-to-ADC-SC1/m-p/1936286#M39852</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2024-08-20T12:43:56Z</dc:date>
    </item>
    <item>
      <title>Re: DMA write to ADC SC1</title>
      <link>https://community.nxp.com/t5/S32K/DMA-write-to-ADC-SC1/m-p/1937524#M39910</link>
      <description>&lt;P&gt;Hi Daniel,&lt;/P&gt;&lt;P&gt;Thanks for your confirmation. It works now.&lt;/P&gt;&lt;P&gt;I had set ADC_SC1_AIEN of the last ADC channel, expecting that last channel exclusively to trigger the DMA. DMA copied then all results in one minor loop. But I re-read the RM and saw that &lt;STRONG&gt;every&lt;/STRONG&gt; COCO triggers the DMA.&lt;/P&gt;&lt;P&gt;SC1 and the PDB were being altered while conversion was still active.&lt;/P&gt;&lt;P&gt;By setting DMA to move one result per minor loop, fixing my mistake, it now works as expected.&lt;/P&gt;</description>
      <pubDate>Wed, 21 Aug 2024 14:30:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/DMA-write-to-ADC-SC1/m-p/1937524#M39910</guid>
      <dc:creator>Joey_van_Hummel</dc:creator>
      <dc:date>2024-08-21T14:30:05Z</dc:date>
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