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  <channel>
    <title>S32K中的主题 LPUART TX DMA issue  S32K1xx</title>
    <link>https://community.nxp.com/t5/S32K/LPUART-TX-DMA-issue-S32K1xx/m-p/1923997#M38694</link>
    <description>&lt;P&gt;&lt;SPAN&gt;I am using S32K146 and using UART TX and RX with DMA. Its working fine most of time but sometime unable to tx as&amp;nbsp;lpuart0_state.isTxBusy doesn't reset to false. As this is rarely occurring, I am unable to reproduce it for debugging. Below are the configuration for UART. Please let me know how to debug it.&amp;nbsp;&lt;BR /&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;-&amp;nbsp;lpuart0_state. transmitStatus is busy&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;-&amp;nbsp;edma_chn_state_t.status is channel normal.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Below are the LPUART0 and DMA register data during the issue&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="chandan_uv_0-1722599758530.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/291714i11F31B50AE8EA018/image-size/medium?v=v2&amp;amp;px=400" role="button" title="chandan_uv_0-1722599758530.png" alt="chandan_uv_0-1722599758530.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="chandan_uv_1-1722599776222.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/291715i2E531D7497A0DEF0/image-size/medium?v=v2&amp;amp;px=400" role="button" title="chandan_uv_1-1722599776222.png" alt="chandan_uv_1-1722599776222.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="chandan_uv_2-1722599782061.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/291717i604A7778F78F5A6A/image-size/medium?v=v2&amp;amp;px=400" role="button" title="chandan_uv_2-1722599782061.png" alt="chandan_uv_2-1722599782061.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="c"&gt;void init_uart(void){
	  status_t ret = STATUS_SUCCESS;

    lpuart_user_config_t lpuart1_cfg;
	
	  edma_init_iot_comm();

    lpuart1_cfg.transferType = LPUART_USING_DMA;
    lpuart1_cfg.baudRate = 1000000; 
    lpuart1_cfg.parityMode = LPUART_PARITY_DISABLED;
    lpuart1_cfg.stopBitCount = LPUART_ONE_STOP_BIT;
    lpuart1_cfg.bitCountPerChar = LPUART_8_BITS_PER_CHAR;
    lpuart1_cfg.rxDMAChannel = EDMA_CHN1_NUMBER;
    lpuart1_cfg.txDMAChannel = EDMA_CHN0_NUMBER;

    ret = LPUART_DRV_Init(UART_COM_4G, &amp;amp;lpuart0_state, &amp;amp;lpuart1_cfg);

    DEV_ASSERT(ret == STATUS_SUCCESS);
	
	  // setLpuartHardFlowCtrl();

    LPUART_DRV_InstallTxCallback(UART_COM_4G, lpuart_tx_callback_t, NULL);

    LPUART_DRV_InstallRxCallback(UART_COM_4G, lpuart_rx_callback_t, NULL);
	
	  LPUART_DRV_ReceiveData(UART_COM_4G, iot_rx_struct.data, MAX_RX_IOT_COMM_BUFFER);
		
		IOT_COMM_UART_FLOW_START_RX;
		
}&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="c"&gt;static status_t edma_init_iot_comm(void){
    status_t ret = STATUS_SUCCESS;
    
    edma_chn_state_t *const edma_channel_states[] = {
        &amp;amp;dma_ctrl_chn0_state,
        &amp;amp;dma_ctrl_chn1_state
    };

    edma_channel_config_t dm_chn0_cfg = {
        .channelPriority = EDMA_CHN_PRIORITY_1,
        .virtChnConfig = EDMA_CHN0_NUMBER,
        .source = EDMA_REQ_LPUART0_TX,
        .callback = NULL,
        .callbackParam = NULL,
        .enableTrigger = false
    };
    
    edma_channel_config_t dm_chn1_cfg = {
        .channelPriority = EDMA_CHN_PRIORITY_0,
        .virtChnConfig = EDMA_CHN1_NUMBER,
        .source = EDMA_REQ_LPUART0_RX,
        .callback = edma_RX_callback, //NULL,
        .callbackParam = NULL,
        .enableTrigger = false
    };
    
    const edma_channel_config_t *const edma_chn_cfg_arr[] = {
        &amp;amp;dm_chn0_cfg,
        &amp;amp;dm_chn1_cfg
    };

    edma_user_config_t dma_ctrl_init_cfg = {
        .chnArbitration = EDMA_ARBITRATION_FIXED_PRIORITY,
        .haltOnError = false
    };
    
    ret = EDMA_DRV_Init(&amp;amp;dma_ctrl_state, &amp;amp;dma_ctrl_init_cfg, edma_channel_states, edma_chn_cfg_arr, EDMA_CONFIGURED_CHANNELS_COUNT);  
    
		DEV_ASSERT(ret == STATUS_SUCCESS);
		
    return ret;
}&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Fri, 02 Aug 2024 11:57:22 GMT</pubDate>
    <dc:creator>chandan_uv</dc:creator>
    <dc:date>2024-08-02T11:57:22Z</dc:date>
    <item>
      <title>LPUART TX DMA issue  S32K1xx</title>
      <link>https://community.nxp.com/t5/S32K/LPUART-TX-DMA-issue-S32K1xx/m-p/1923997#M38694</link>
      <description>&lt;P&gt;&lt;SPAN&gt;I am using S32K146 and using UART TX and RX with DMA. Its working fine most of time but sometime unable to tx as&amp;nbsp;lpuart0_state.isTxBusy doesn't reset to false. As this is rarely occurring, I am unable to reproduce it for debugging. Below are the configuration for UART. Please let me know how to debug it.&amp;nbsp;&lt;BR /&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;-&amp;nbsp;lpuart0_state. transmitStatus is busy&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;-&amp;nbsp;edma_chn_state_t.status is channel normal.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Below are the LPUART0 and DMA register data during the issue&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="chandan_uv_0-1722599758530.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/291714i11F31B50AE8EA018/image-size/medium?v=v2&amp;amp;px=400" role="button" title="chandan_uv_0-1722599758530.png" alt="chandan_uv_0-1722599758530.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="chandan_uv_1-1722599776222.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/291715i2E531D7497A0DEF0/image-size/medium?v=v2&amp;amp;px=400" role="button" title="chandan_uv_1-1722599776222.png" alt="chandan_uv_1-1722599776222.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="chandan_uv_2-1722599782061.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/291717i604A7778F78F5A6A/image-size/medium?v=v2&amp;amp;px=400" role="button" title="chandan_uv_2-1722599782061.png" alt="chandan_uv_2-1722599782061.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="c"&gt;void init_uart(void){
	  status_t ret = STATUS_SUCCESS;

    lpuart_user_config_t lpuart1_cfg;
	
	  edma_init_iot_comm();

    lpuart1_cfg.transferType = LPUART_USING_DMA;
    lpuart1_cfg.baudRate = 1000000; 
    lpuart1_cfg.parityMode = LPUART_PARITY_DISABLED;
    lpuart1_cfg.stopBitCount = LPUART_ONE_STOP_BIT;
    lpuart1_cfg.bitCountPerChar = LPUART_8_BITS_PER_CHAR;
    lpuart1_cfg.rxDMAChannel = EDMA_CHN1_NUMBER;
    lpuart1_cfg.txDMAChannel = EDMA_CHN0_NUMBER;

    ret = LPUART_DRV_Init(UART_COM_4G, &amp;amp;lpuart0_state, &amp;amp;lpuart1_cfg);

    DEV_ASSERT(ret == STATUS_SUCCESS);
	
	  // setLpuartHardFlowCtrl();

    LPUART_DRV_InstallTxCallback(UART_COM_4G, lpuart_tx_callback_t, NULL);

    LPUART_DRV_InstallRxCallback(UART_COM_4G, lpuart_rx_callback_t, NULL);
	
	  LPUART_DRV_ReceiveData(UART_COM_4G, iot_rx_struct.data, MAX_RX_IOT_COMM_BUFFER);
		
		IOT_COMM_UART_FLOW_START_RX;
		
}&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="c"&gt;static status_t edma_init_iot_comm(void){
    status_t ret = STATUS_SUCCESS;
    
    edma_chn_state_t *const edma_channel_states[] = {
        &amp;amp;dma_ctrl_chn0_state,
        &amp;amp;dma_ctrl_chn1_state
    };

    edma_channel_config_t dm_chn0_cfg = {
        .channelPriority = EDMA_CHN_PRIORITY_1,
        .virtChnConfig = EDMA_CHN0_NUMBER,
        .source = EDMA_REQ_LPUART0_TX,
        .callback = NULL,
        .callbackParam = NULL,
        .enableTrigger = false
    };
    
    edma_channel_config_t dm_chn1_cfg = {
        .channelPriority = EDMA_CHN_PRIORITY_0,
        .virtChnConfig = EDMA_CHN1_NUMBER,
        .source = EDMA_REQ_LPUART0_RX,
        .callback = edma_RX_callback, //NULL,
        .callbackParam = NULL,
        .enableTrigger = false
    };
    
    const edma_channel_config_t *const edma_chn_cfg_arr[] = {
        &amp;amp;dm_chn0_cfg,
        &amp;amp;dm_chn1_cfg
    };

    edma_user_config_t dma_ctrl_init_cfg = {
        .chnArbitration = EDMA_ARBITRATION_FIXED_PRIORITY,
        .haltOnError = false
    };
    
    ret = EDMA_DRV_Init(&amp;amp;dma_ctrl_state, &amp;amp;dma_ctrl_init_cfg, edma_channel_states, edma_chn_cfg_arr, EDMA_CONFIGURED_CHANNELS_COUNT);  
    
		DEV_ASSERT(ret == STATUS_SUCCESS);
		
    return ret;
}&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 02 Aug 2024 11:57:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/LPUART-TX-DMA-issue-S32K1xx/m-p/1923997#M38694</guid>
      <dc:creator>chandan_uv</dc:creator>
      <dc:date>2024-08-02T11:57:22Z</dc:date>
    </item>
    <item>
      <title>Re: LPUART TX DMA issue  S32K1xx</title>
      <link>https://community.nxp.com/t5/S32K/LPUART-TX-DMA-issue-S32K1xx/m-p/1925305#M38910</link>
      <description>&lt;P&gt;I debugged more during the issue&lt;/P&gt;&lt;P&gt;- LPUART DMA TX request bit is still set&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="chandan_uv_0-1722859500498.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/291942iBB849BBAC9481326/image-size/medium?v=v2&amp;amp;px=400" role="button" title="chandan_uv_0-1722859500498.png" alt="chandan_uv_0-1722859500498.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;- In DMA, DMA request signal bit is 0&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="chandan_uv_1-1722859560919.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/291943i887E59720ED9AF1E/image-size/medium?v=v2&amp;amp;px=400" role="button" title="chandan_uv_1-1722859560919.png" alt="chandan_uv_1-1722859560919.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 05 Aug 2024 12:06:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/LPUART-TX-DMA-issue-S32K1xx/m-p/1925305#M38910</guid>
      <dc:creator>chandan_uv</dc:creator>
      <dc:date>2024-08-05T12:06:34Z</dc:date>
    </item>
    <item>
      <title>Re: LPUART TX DMA issue  S32K1xx</title>
      <link>https://community.nxp.com/t5/S32K/LPUART-TX-DMA-issue-S32K1xx/m-p/1934620#M39760</link>
      <description>&lt;P&gt;&lt;A href="mailto:Hi@chandan_uv" target="_blank"&gt;Hi@chandan_uv&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;We are currently overloaded and response times are slow, thank you for your understanding.&lt;/P&gt;
&lt;P&gt;Can you provide a demo so we can reproduce your issue?&lt;/P&gt;</description>
      <pubDate>Mon, 19 Aug 2024 01:58:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/LPUART-TX-DMA-issue-S32K1xx/m-p/1934620#M39760</guid>
      <dc:creator>Senlent</dc:creator>
      <dc:date>2024-08-19T01:58:52Z</dc:date>
    </item>
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