topic Re: compiling error: S32K344 After D_CACHE_ENABLE is enabled in S32K

compiling error: S32K344 After D_CACHE_ENABLE is enabled

harryoceana — Tue, 16 Jul 2024 03:10:43 GMT

RTD 3.0.0 P07

S32DS 3.5

S32K344 After D_CACHE_ENABLE is enabled, the following error occurs when compiling. The cc.h file has many undefined macros

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Re: compiling error: S32K344 After D_CACHE_ENABLE is enabled

Senlent — Thu, 18 Jul 2024 07:49:20 GMT

Hi@harryoceana

Could you please describe clearly where the demo you are using comes from, what its name is, and what modifications you have made to it, so that we can reproduce the problem.

Re: compiling error: S32K344 After D_CACHE_ENABLE is enabled

harryoceana — Thu, 18 Jul 2024 09:08:01 GMT

This is LWIP example, Only the D_CACHE_ENABLE definition was added .

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Re: compiling error: S32K344 After D_CACHE_ENABLE is enabled

Senlent — Thu, 18 Jul 2024 10:06:37 GMT

Hi@harryoceana

D-cache is not supported in this routine, if you want to enable D-cache, this is suggestion from SW team.
You can add some following macros:

/* Data Cache masks */ #define DCACHE_CCR_EN_MASK ((uint32)1U << 16U) #define DCACHE_CSSELR_EN(x) ((uint32)((x) & (~1U))) #define DCACHE_DCCXSW_SET_MASK ((uint32)0x3FE0U) #define DCACHE_DCCXSW_SET_SHIFT ((uint32)5U) #define DCACHE_DCCXSW_WAY_MASK ((uint32)0xC0000000U) #define DCACHE_DCCXSW_WAY_SHIFT ((uint32)30U) /* Instruction Cache masks */ #define ICACHE_CCR_EN_MASK ((uint32)1U << 17U) #define ICACHE_CSSELR_EN(x) ((uint32)((x) | 1U)) /* Cache set, way and line size */ #define CACHE_CCSIDR_SET_MASK ((uint32)0xFFFE000U) #define CACHE_CCSIDR_SET_SHIFT ((uint32)13U) #define CACHE_CCSIDR_SET_SIZE(x) ((uint32)((((uint32)(x) & CACHE_CCSIDR_SET_MASK) >> CACHE_CCSIDR_SET_SHIFT) + 1U)) #define CACHE_CCSIDR_WAY_MASK ((uint32)0x1FF8U) #define CACHE_CCSIDR_WAY_SHIFT ((uint32)3U) #define CACHE_CCSIDR_WAY_SIZE(x) ((uint32)((((uint32)(x) & CACHE_CCSIDR_WAY_MASK) >> CACHE_CCSIDR_WAY_SHIFT) + 1U)) #define CACHE_CCSIDR_LINE_SIZE_MASK ((uint32)0x7U) #define CACHE_CCSIDR_LINE_SHIFT ((uint32)0U) #define CACHE_CCSIDR_LINE_SIZE(x) ((uint32)((((((uint32)(x) & CACHE_CCSIDR_LINE_SIZE_MASK) >> CACHE_CCSIDR_LINE_SHIFT) + 1U) * 4U) * 4U))

Test:

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