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    <title>S32KのトピックS32K312 sending error using Flexio SPI as master node</title>
    <link>https://community.nxp.com/t5/S32K/S32K312-sending-error-using-Flexio-SPI-as-master-node/m-p/1906802#M37621</link>
    <description>&lt;P&gt;1.Development environment:S32DS3.5&lt;/P&gt;&lt;P&gt;2.RTD version:4.0.0&lt;/P&gt;&lt;P&gt;3. Refer to the rtd 2.0.3 routine code, detailed code is attached&lt;/P&gt;&lt;P&gt;4. Expected goals such as 4.1 and 4.2&lt;/P&gt;&lt;P&gt;4.1 MOSI only sends data once, while MISO does not receive data&lt;/P&gt;&lt;P&gt;4.2 MOSI triggers the chip selection pin once for every byte of data sent&lt;/P&gt;&lt;P&gt;5. Actual phenomena such as 5.1, 5.2, 5.3, and 5.4&lt;/P&gt;&lt;P&gt;5.1 MOSI keeps sending data, while MISO keeps receiving data&lt;/P&gt;&lt;P&gt;5.2 MOSI triggers the chip selection pin once every 4 bytes of data sent&lt;/P&gt;&lt;P&gt;5.3 Thumbnails&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="victory_0-1720765461786.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/288258iAA13186B5CA9A0CF/image-size/medium?v=v2&amp;amp;px=400" role="button" title="victory_0-1720765461786.png" alt="victory_0-1720765461786.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;5.4 Unfolding Diagram&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="victory_1-1720765482905.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/288259i62DCEEDA646EB144/image-size/medium?v=v2&amp;amp;px=400" role="button" title="victory_1-1720765482905.png" alt="victory_1-1720765482905.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;6.Main. c is as follows&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#include&lt;/SPAN&gt; &lt;SPAN&gt;"Mcal.h"&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#include&lt;/SPAN&gt; &lt;SPAN&gt;"Clock_Ip.h"&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#include&lt;/SPAN&gt; &lt;SPAN&gt;"Siul2_Port_Ip.h"&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#include&lt;/SPAN&gt; &lt;SPAN&gt;"Siul2_Dio_Ip.h"&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#include&lt;/SPAN&gt; &lt;SPAN&gt;"IntCtrl_Ip.h"&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#include&lt;/SPAN&gt; &lt;SPAN&gt;"Flexio_Mcl_Ip.h"&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#include&lt;/SPAN&gt; &lt;SPAN&gt;"Flexio_Spi_Ip.h"&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;/* Time to transfer all frame data */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#define&lt;/SPAN&gt; &lt;SPAN&gt;TIMEOUT&lt;/SPAN&gt;&lt;SPAN&gt; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ((uint32)&lt;/SPAN&gt;&lt;SPAN&gt;1000000UL&lt;/SPAN&gt;&lt;SPAN&gt;)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;static&lt;/SPAN&gt; &lt;SPAN&gt;uint8_t&lt;/SPAN&gt; &lt;SPAN&gt;data_out&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;10&lt;/SPAN&gt;&lt;SPAN&gt;] = {&lt;/SPAN&gt;&lt;SPAN&gt;0x1&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;0x2&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;3&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;4&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;5&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;6&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;7&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;8&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;9&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;10&lt;/SPAN&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;SPAN&gt; /* Transmission buffer. */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;static&lt;/SPAN&gt; &lt;SPAN&gt;uint8_t&lt;/SPAN&gt; &lt;SPAN&gt;data_in&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;10&lt;/SPAN&gt;&lt;SPAN&gt;] = {&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;SPAN&gt; /* Buffer for receiving. */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;#define&lt;/SPAN&gt; &lt;SPAN&gt;MASTER_EXTERNAL_DEVICE&lt;/SPAN&gt;&lt;SPAN&gt; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; (&lt;/SPAN&gt;&lt;SPAN&gt;Flexio_Spi_Ip_DeviceAttributes_SpiExternalDevice_0_Instance_0&lt;/SPAN&gt;&lt;SPAN&gt;)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;int&lt;/SPAN&gt; &lt;SPAN&gt;main&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;void&lt;/SPAN&gt;&lt;SPAN&gt;)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;uint32_t&lt;/SPAN&gt; &lt;SPAN&gt;Counter&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;0xFFFFFF&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; /** Clock IPL Init */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;Clock_Ip_Init&lt;/SPAN&gt;&lt;SPAN&gt;(&amp;amp;&lt;/SPAN&gt;&lt;SPAN&gt;Clock_Ip_aClockConfig&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;]);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; /** siul2 pins init */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;Siul2_Port_Ip_Init&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;NUM_OF_CONFIGURED_PINS_PortContainer_0_BOARD_InitPeripherals&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;\&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;g_pin_mux_InitConfigArr_PortContainer_0_BOARD_InitPeripherals&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;IntCtrl_Ip_Init&lt;/SPAN&gt;&lt;SPAN&gt;(&amp;amp;&lt;/SPAN&gt;&lt;SPAN&gt;IntCtrlConfig_0&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;Flexio_Mcl_Ip_InitDevice&lt;/SPAN&gt;&lt;SPAN&gt;(&amp;amp;&lt;/SPAN&gt;&lt;SPAN&gt;Flexio_Ip_xFlexioInit&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;Flexio_Spi_Ip_Init&lt;/SPAN&gt;&lt;SPAN&gt;(&amp;amp;&lt;/SPAN&gt;&lt;SPAN&gt;Flexio_Spi_Ip_PhyUnitConfig_SpiPhyUnit_0_Instance_0&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; /* Update Framesize */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;Flexio_Spi_Ip_UpdateFrameSize&lt;/SPAN&gt;&lt;SPAN&gt;(&amp;amp;&lt;/SPAN&gt;&lt;SPAN&gt;MASTER_EXTERNAL_DEVICE&lt;/SPAN&gt;&lt;SPAN&gt;, &lt;/SPAN&gt;&lt;SPAN&gt;16U&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; /* Update Transfered Bit order */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;Flexio_Spi_Ip_UpdateLsb&lt;/SPAN&gt;&lt;SPAN&gt;(&amp;amp;&lt;/SPAN&gt;&lt;SPAN&gt;MASTER_EXTERNAL_DEVICE&lt;/SPAN&gt;&lt;SPAN&gt;, &lt;/SPAN&gt;&lt;SPAN&gt;FALSE&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;Flexio_Spi_Ip_SyncTransmit&lt;/SPAN&gt;&lt;SPAN&gt;(&amp;amp;&lt;/SPAN&gt;&lt;SPAN&gt;MASTER_EXTERNAL_DEVICE&lt;/SPAN&gt;&lt;SPAN&gt;, &lt;/SPAN&gt;&lt;SPAN&gt;data_out&lt;/SPAN&gt;&lt;SPAN&gt;, &lt;/SPAN&gt;&lt;SPAN&gt;data_in&lt;/SPAN&gt;&lt;SPAN&gt;, &lt;/SPAN&gt;&lt;SPAN&gt;10&lt;/SPAN&gt;&lt;SPAN&gt;, &lt;/SPAN&gt;&lt;SPAN&gt;TIMEOUT&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;while&lt;/SPAN&gt;&lt;SPAN&gt; (&lt;/SPAN&gt;&lt;SPAN&gt;FLEXIO_SPI_IP_IDLE&lt;/SPAN&gt;&lt;SPAN&gt; != &lt;/SPAN&gt;&lt;SPAN&gt;Flexio_Spi_Ip_GetStatus&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;MASTER_EXTERNAL_DEVICE&lt;/SPAN&gt;&lt;SPAN&gt;.&lt;/SPAN&gt;&lt;SPAN&gt;Instance&lt;/SPAN&gt;&lt;SPAN&gt;));&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;7.The software related configurations are as follows&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;7.PIN&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="victory_2-1720765588032.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/288261i87376D2DC3B14B8A/image-size/medium?v=v2&amp;amp;px=400" role="button" title="victory_2-1720765588032.png" alt="victory_2-1720765588032.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;7.2flexio_spi&lt;/P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="victory_3-1720765644833.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/288262iF68A147E979FB3D3/image-size/medium?v=v2&amp;amp;px=400" role="button" title="victory_3-1720765644833.png" alt="victory_3-1720765644833.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="victory_4-1720765666996.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/288263i2AFA5938EC244949/image-size/medium?v=v2&amp;amp;px=400" role="button" title="victory_4-1720765666996.png" alt="victory_4-1720765666996.png" /&gt;&lt;/span&gt;&lt;P&gt;7.3 flexio_mcl_ip&lt;/P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="victory_5-1720765771354.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/288264i141EA815951F08C9/image-size/medium?v=v2&amp;amp;px=400" role="button" title="victory_5-1720765771354.png" alt="victory_5-1720765771354.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="victory_6-1720765788318.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/288265iAF16C5445162FA35/image-size/medium?v=v2&amp;amp;px=400" role="button" title="victory_6-1720765788318.png" alt="victory_6-1720765788318.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Above,thanks!&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
    <pubDate>Fri, 12 Jul 2024 06:31:19 GMT</pubDate>
    <dc:creator>victory</dc:creator>
    <dc:date>2024-07-12T06:31:19Z</dc:date>
    <item>
      <title>S32K312 sending error using Flexio SPI as master node</title>
      <link>https://community.nxp.com/t5/S32K/S32K312-sending-error-using-Flexio-SPI-as-master-node/m-p/1906802#M37621</link>
      <description>&lt;P&gt;1.Development environment:S32DS3.5&lt;/P&gt;&lt;P&gt;2.RTD version:4.0.0&lt;/P&gt;&lt;P&gt;3. Refer to the rtd 2.0.3 routine code, detailed code is attached&lt;/P&gt;&lt;P&gt;4. Expected goals such as 4.1 and 4.2&lt;/P&gt;&lt;P&gt;4.1 MOSI only sends data once, while MISO does not receive data&lt;/P&gt;&lt;P&gt;4.2 MOSI triggers the chip selection pin once for every byte of data sent&lt;/P&gt;&lt;P&gt;5. Actual phenomena such as 5.1, 5.2, 5.3, and 5.4&lt;/P&gt;&lt;P&gt;5.1 MOSI keeps sending data, while MISO keeps receiving data&lt;/P&gt;&lt;P&gt;5.2 MOSI triggers the chip selection pin once every 4 bytes of data sent&lt;/P&gt;&lt;P&gt;5.3 Thumbnails&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="victory_0-1720765461786.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/288258iAA13186B5CA9A0CF/image-size/medium?v=v2&amp;amp;px=400" role="button" title="victory_0-1720765461786.png" alt="victory_0-1720765461786.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;5.4 Unfolding Diagram&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="victory_1-1720765482905.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/288259i62DCEEDA646EB144/image-size/medium?v=v2&amp;amp;px=400" role="button" title="victory_1-1720765482905.png" alt="victory_1-1720765482905.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;6.Main. c is as follows&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#include&lt;/SPAN&gt; &lt;SPAN&gt;"Mcal.h"&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#include&lt;/SPAN&gt; &lt;SPAN&gt;"Clock_Ip.h"&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#include&lt;/SPAN&gt; &lt;SPAN&gt;"Siul2_Port_Ip.h"&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#include&lt;/SPAN&gt; &lt;SPAN&gt;"Siul2_Dio_Ip.h"&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#include&lt;/SPAN&gt; &lt;SPAN&gt;"IntCtrl_Ip.h"&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#include&lt;/SPAN&gt; &lt;SPAN&gt;"Flexio_Mcl_Ip.h"&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#include&lt;/SPAN&gt; &lt;SPAN&gt;"Flexio_Spi_Ip.h"&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;/* Time to transfer all frame data */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#define&lt;/SPAN&gt; &lt;SPAN&gt;TIMEOUT&lt;/SPAN&gt;&lt;SPAN&gt; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; ((uint32)&lt;/SPAN&gt;&lt;SPAN&gt;1000000UL&lt;/SPAN&gt;&lt;SPAN&gt;)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;static&lt;/SPAN&gt; &lt;SPAN&gt;uint8_t&lt;/SPAN&gt; &lt;SPAN&gt;data_out&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;10&lt;/SPAN&gt;&lt;SPAN&gt;] = {&lt;/SPAN&gt;&lt;SPAN&gt;0x1&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;0x2&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;3&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;4&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;5&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;6&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;7&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;8&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;9&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;10&lt;/SPAN&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;SPAN&gt; /* Transmission buffer. */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;static&lt;/SPAN&gt; &lt;SPAN&gt;uint8_t&lt;/SPAN&gt; &lt;SPAN&gt;data_in&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;10&lt;/SPAN&gt;&lt;SPAN&gt;] = {&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;SPAN&gt; /* Buffer for receiving. */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;#define&lt;/SPAN&gt; &lt;SPAN&gt;MASTER_EXTERNAL_DEVICE&lt;/SPAN&gt;&lt;SPAN&gt; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; (&lt;/SPAN&gt;&lt;SPAN&gt;Flexio_Spi_Ip_DeviceAttributes_SpiExternalDevice_0_Instance_0&lt;/SPAN&gt;&lt;SPAN&gt;)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;int&lt;/SPAN&gt; &lt;SPAN&gt;main&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;void&lt;/SPAN&gt;&lt;SPAN&gt;)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;uint32_t&lt;/SPAN&gt; &lt;SPAN&gt;Counter&lt;/SPAN&gt;&lt;SPAN&gt; = &lt;/SPAN&gt;&lt;SPAN&gt;0xFFFFFF&lt;/SPAN&gt;&lt;SPAN&gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; /** Clock IPL Init */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;Clock_Ip_Init&lt;/SPAN&gt;&lt;SPAN&gt;(&amp;amp;&lt;/SPAN&gt;&lt;SPAN&gt;Clock_Ip_aClockConfig&lt;/SPAN&gt;&lt;SPAN&gt;[&lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;SPAN&gt;]);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; /** siul2 pins init */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;Siul2_Port_Ip_Init&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;NUM_OF_CONFIGURED_PINS_PortContainer_0_BOARD_InitPeripherals&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;\&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;g_pin_mux_InitConfigArr_PortContainer_0_BOARD_InitPeripherals&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;IntCtrl_Ip_Init&lt;/SPAN&gt;&lt;SPAN&gt;(&amp;amp;&lt;/SPAN&gt;&lt;SPAN&gt;IntCtrlConfig_0&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;Flexio_Mcl_Ip_InitDevice&lt;/SPAN&gt;&lt;SPAN&gt;(&amp;amp;&lt;/SPAN&gt;&lt;SPAN&gt;Flexio_Ip_xFlexioInit&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;Flexio_Spi_Ip_Init&lt;/SPAN&gt;&lt;SPAN&gt;(&amp;amp;&lt;/SPAN&gt;&lt;SPAN&gt;Flexio_Spi_Ip_PhyUnitConfig_SpiPhyUnit_0_Instance_0&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; /* Update Framesize */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;Flexio_Spi_Ip_UpdateFrameSize&lt;/SPAN&gt;&lt;SPAN&gt;(&amp;amp;&lt;/SPAN&gt;&lt;SPAN&gt;MASTER_EXTERNAL_DEVICE&lt;/SPAN&gt;&lt;SPAN&gt;, &lt;/SPAN&gt;&lt;SPAN&gt;16U&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; /* Update Transfered Bit order */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;Flexio_Spi_Ip_UpdateLsb&lt;/SPAN&gt;&lt;SPAN&gt;(&amp;amp;&lt;/SPAN&gt;&lt;SPAN&gt;MASTER_EXTERNAL_DEVICE&lt;/SPAN&gt;&lt;SPAN&gt;, &lt;/SPAN&gt;&lt;SPAN&gt;FALSE&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;Flexio_Spi_Ip_SyncTransmit&lt;/SPAN&gt;&lt;SPAN&gt;(&amp;amp;&lt;/SPAN&gt;&lt;SPAN&gt;MASTER_EXTERNAL_DEVICE&lt;/SPAN&gt;&lt;SPAN&gt;, &lt;/SPAN&gt;&lt;SPAN&gt;data_out&lt;/SPAN&gt;&lt;SPAN&gt;, &lt;/SPAN&gt;&lt;SPAN&gt;data_in&lt;/SPAN&gt;&lt;SPAN&gt;, &lt;/SPAN&gt;&lt;SPAN&gt;10&lt;/SPAN&gt;&lt;SPAN&gt;, &lt;/SPAN&gt;&lt;SPAN&gt;TIMEOUT&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;while&lt;/SPAN&gt;&lt;SPAN&gt; (&lt;/SPAN&gt;&lt;SPAN&gt;FLEXIO_SPI_IP_IDLE&lt;/SPAN&gt;&lt;SPAN&gt; != &lt;/SPAN&gt;&lt;SPAN&gt;Flexio_Spi_Ip_GetStatus&lt;/SPAN&gt;&lt;SPAN&gt;(&lt;/SPAN&gt;&lt;SPAN&gt;MASTER_EXTERNAL_DEVICE&lt;/SPAN&gt;&lt;SPAN&gt;.&lt;/SPAN&gt;&lt;SPAN&gt;Instance&lt;/SPAN&gt;&lt;SPAN&gt;));&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;7.The software related configurations are as follows&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;7.PIN&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="victory_2-1720765588032.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/288261i87376D2DC3B14B8A/image-size/medium?v=v2&amp;amp;px=400" role="button" title="victory_2-1720765588032.png" alt="victory_2-1720765588032.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;7.2flexio_spi&lt;/P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="victory_3-1720765644833.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/288262iF68A147E979FB3D3/image-size/medium?v=v2&amp;amp;px=400" role="button" title="victory_3-1720765644833.png" alt="victory_3-1720765644833.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="victory_4-1720765666996.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/288263i2AFA5938EC244949/image-size/medium?v=v2&amp;amp;px=400" role="button" title="victory_4-1720765666996.png" alt="victory_4-1720765666996.png" /&gt;&lt;/span&gt;&lt;P&gt;7.3 flexio_mcl_ip&lt;/P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="victory_5-1720765771354.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/288264i141EA815951F08C9/image-size/medium?v=v2&amp;amp;px=400" role="button" title="victory_5-1720765771354.png" alt="victory_5-1720765771354.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="victory_6-1720765788318.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/288265iAF16C5445162FA35/image-size/medium?v=v2&amp;amp;px=400" role="button" title="victory_6-1720765788318.png" alt="victory_6-1720765788318.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Above,thanks!&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Fri, 12 Jul 2024 06:31:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K312-sending-error-using-Flexio-SPI-as-master-node/m-p/1906802#M37621</guid>
      <dc:creator>victory</dc:creator>
      <dc:date>2024-07-12T06:31:19Z</dc:date>
    </item>
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