S32KのトピックS32K146 ADC

S32K146 ADC

Stefanescu — Thu, 13 Jun 2024 19:02:01 GMT

Hello.

I am trying to configure 2 different ADC hardware units(0,1) using DMA hardware trigger LPIT(interrupt at 2ms) as input and PDB0,1 as output. VREFL(ch29) and VREFH(ch30) are in first ADC hardware unit, no sequence error is set on PDB0 but the values i received on configured buffer are not stable. ADC clock is set at 40MH but the values read on VREFH are between 8 and 11.5V. Is there any specific configuration that i can check in order to stable the values read.

Re: S32K146 ADC

Senlent — Fri, 14 Jun 2024 09:03:39 GMT

Hi@Stefanescu

“DC clock is set at 40MH but the values read on VREFH are between 8 and 11.5V”

I am a little confused. It is impossible for the S32K1's VREFL and VREFH to reach such a high voltage.

I made a test demo according to your requirements. I tested the two internal channels VREFL and VREFH.

The values I sampled were very stable.

Re: S32K146 ADC

Stefanescu — Mon, 17 Jun 2024 12:21:02 GMT

Thank you for your fast reply. I found the problem, I was using a S32K146 but ResourceSubderivative was set to 144, and the ADCH registers were configured wrong due to ADCH_WIDTH used for 144. I thought that only memory size was different but apparently not. Now raw value for VREFH is 1023, the problem now is that ADC only reads values on internal channels and not to external configured ones.