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    <title>S32K中的主题 Re: S32K312 send uart data fail</title>
    <link>https://community.nxp.com/t5/S32K/S32K312-send-uart-data-fail/m-p/1877800#M35992</link>
    <description>&lt;P&gt;Hi, thank you for reply, I tried to disable the whole dcache before uart test, but the problem hadn't been solved.&lt;/P&gt;&lt;DIV&gt;/*start uart dma rx*/&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;UartRxDmaStart(6U, UART_CONFIG.RxDMAChannel);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;Mcl_CacheDisable(MCL_CACHE_LMEM,MCL_CACHE_ALL_BUS);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;Mcl_CacheDisable(MCL_CACHE_CORE,MCL_CACHE_ALL_BUS);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; /**************************************************/&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; /* Main example loop&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; /**************************************************/&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; while(1)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; {&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; //UartSend(6u,UART_CONFIG.TxDMAChannel,rxdata, 10);&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; UartReceive(6u,UART_CONFIG.RxDMAChannel,rxdata,&amp;amp;rxlen,100U);&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;if(rxlen &amp;gt; 0)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;UartSend(6u,UART_CONFIG.TxDMAChannel,rxdata, rxlen);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; }&lt;/DIV&gt;</description>
    <pubDate>Thu, 30 May 2024 03:04:40 GMT</pubDate>
    <dc:creator>jhuang1</dc:creator>
    <dc:date>2024-05-30T03:04:40Z</dc:date>
    <item>
      <title>S32K312 send uart data fail</title>
      <link>https://community.nxp.com/t5/S32K/S32K312-send-uart-data-fail/m-p/1876094#M35875</link>
      <description>&lt;P&gt;Hello, I want to send data via uart + dma, and the program works fine on RTD 2.0.3. But when I transport it to RTD 4.0.0, the uart can only recieve data successfully, it sent "00" always at the trasmitting side. The test program I uploaded recieves data and transmit them out, it can recieve right fix data like 0~16, but transmit 16 zeros. please help me to check the program, thanks.&lt;/P&gt;</description>
      <pubDate>Tue, 28 May 2024 08:13:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K312-send-uart-data-fail/m-p/1876094#M35875</guid>
      <dc:creator>jhuang1</dc:creator>
      <dc:date>2024-05-28T08:13:32Z</dc:date>
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    <item>
      <title>Re: S32K312 send uart data fail</title>
      <link>https://community.nxp.com/t5/S32K/S32K312-send-uart-data-fail/m-p/1877780#M35988</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Please place the buffer in a non cacheable memory section.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;In the DMA transfer mode, DMA transfers may have cache coherency problems. To avoid possible coherency issues when D-CACHE is enabled, the user shall ensure that the buffers used as TCD source and destination are allocated in the NON-CACHEABLE area (by means of Uart_Memmap). Otherwise, the Uart driver has some dependencies. User must to put all variables, which were used for transmitter and receiver, in the NON CACHEABLE memory section in the RAM zone by the definition UART_START_SEC_VAR_&amp;lt;INIT_POLICY&amp;gt;_&amp;lt;ALIGNMENT&amp;gt;_NO_CACHEABLE and UART_STOP_SEC_VAR_&amp;lt;INIT_POLICY&amp;gt;_&amp;lt;ALIGNMENT&amp;gt;_NO_CACHEABLE.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DMA transfer mode buffer D-CACHE enabled NON-CACHEABLE.png" style="width: 895px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/281631iB6AA5E1D65805FB2/image-size/large?v=v2&amp;amp;px=999" role="button" title="DMA transfer mode buffer D-CACHE enabled NON-CACHEABLE.png" alt="DMA transfer mode buffer D-CACHE enabled NON-CACHEABLE.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;Best Regards,&lt;BR /&gt;Robin&lt;BR /&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;
&lt;P&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt;Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;</description>
      <pubDate>Thu, 30 May 2024 02:45:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K312-send-uart-data-fail/m-p/1877780#M35988</guid>
      <dc:creator>Robin_Shen</dc:creator>
      <dc:date>2024-05-30T02:45:01Z</dc:date>
    </item>
    <item>
      <title>Re: S32K312 send uart data fail</title>
      <link>https://community.nxp.com/t5/S32K/S32K312-send-uart-data-fail/m-p/1877800#M35992</link>
      <description>&lt;P&gt;Hi, thank you for reply, I tried to disable the whole dcache before uart test, but the problem hadn't been solved.&lt;/P&gt;&lt;DIV&gt;/*start uart dma rx*/&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;UartRxDmaStart(6U, UART_CONFIG.RxDMAChannel);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;Mcl_CacheDisable(MCL_CACHE_LMEM,MCL_CACHE_ALL_BUS);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;Mcl_CacheDisable(MCL_CACHE_CORE,MCL_CACHE_ALL_BUS);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; /**************************************************/&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; /* Main example loop&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; /**************************************************/&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; while(1)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; {&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; //UartSend(6u,UART_CONFIG.TxDMAChannel,rxdata, 10);&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; UartReceive(6u,UART_CONFIG.RxDMAChannel,rxdata,&amp;amp;rxlen,100U);&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;if(rxlen &amp;gt; 0)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;UartSend(6u,UART_CONFIG.TxDMAChannel,rxdata, rxlen);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; }&lt;/DIV&gt;</description>
      <pubDate>Thu, 30 May 2024 03:04:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K312-send-uart-data-fail/m-p/1877800#M35992</guid>
      <dc:creator>jhuang1</dc:creator>
      <dc:date>2024-05-30T03:04:40Z</dc:date>
    </item>
    <item>
      <title>Re: S32K312 send uart data fail</title>
      <link>https://community.nxp.com/t5/S32K/S32K312-send-uart-data-fail/m-p/1881250#M36234</link>
      <description>&lt;P&gt;If it works properly after delete &lt;STRONG&gt;D_CACHE_ENABLE&lt;/STRONG&gt; in &lt;STRONG&gt;&lt;EM&gt;Defined symbols&lt;/EM&gt;&lt;/STRONG&gt;, then it should be related to data cache.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="D_CACHE_ENABLE DMA UART.png" style="width: 813px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/282550i12039E7F5A0F62E8/image-size/large?v=v2&amp;amp;px=999" role="button" title="D_CACHE_ENABLE DMA UART.png" alt="D_CACHE_ENABLE DMA UART.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Try putting the&amp;nbsp;buffer in a non cacheable memory section:&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;#define UART_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE&lt;BR /&gt;#include "Uart_MemMap.h"&lt;BR /&gt;__attribute__(( aligned(32) )) uint8 rxdata[256u];&lt;/P&gt;
&lt;P&gt;#define UART_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE&lt;BR /&gt;#include "Uart_MemMap.h"&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Are &lt;STRONG&gt;UartSend&lt;/STRONG&gt; and &lt;STRONG&gt;UartReceive&lt;/STRONG&gt; your own APIs? Do S32K3 RTD APIs such as &lt;STRONG&gt;Uart_AsyncSend&lt;/STRONG&gt; and &lt;STRONG&gt;Uart_AsyncReceive&lt;/STRONG&gt; work properly?&lt;/P&gt;</description>
      <pubDate>Wed, 05 Jun 2024 06:42:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/S32K312-send-uart-data-fail/m-p/1881250#M36234</guid>
      <dc:creator>Robin_Shen</dc:creator>
      <dc:date>2024-06-05T06:42:02Z</dc:date>
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