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    <title>topic Re: Emios interrupt on a Center Aligned Output PWM with Dead Time Insertion Buffered channel in S32K</title>
    <link>https://community.nxp.com/t5/S32K/Emios-interrupt-on-a-Center-Aligned-Output-PWM-with-Dead-Time/m-p/1877238#M35958</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;eMIOS channel interrupt is enabled in channel Control register's FEN bit. If set (and DMA bit is cleared) interrupt request to core is triggered when Sn[FLAG] is set.&amp;nbsp;&lt;BR /&gt;In OPWMCB mode flag is set either on training edge or both edges, based on MODE field setting.&lt;/P&gt;
&lt;P&gt;BR, Petr&lt;/P&gt;</description>
    <pubDate>Wed, 29 May 2024 11:23:58 GMT</pubDate>
    <dc:creator>PetrS</dc:creator>
    <dc:date>2024-05-29T11:23:58Z</dc:date>
    <item>
      <title>Emios interrupt on a Center Aligned Output PWM with Dead Time Insertion Buffered channel</title>
      <link>https://community.nxp.com/t5/S32K/Emios-interrupt-on-a-Center-Aligned-Output-PWM-with-Dead-Time/m-p/1876367#M35898</link>
      <description>&lt;P&gt;I would like to implement an interrupt in a flank of an eMios channel that is operating under the Center Aligned Output PWM with Dead Time Insertion Buffered (OPWMCB) mode. It is possible to do it. I'm reading the Reference manual but haven't found the way to doit. I which register you confiture the interrupt functionality?&lt;/P&gt;</description>
      <pubDate>Tue, 28 May 2024 13:57:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Emios-interrupt-on-a-Center-Aligned-Output-PWM-with-Dead-Time/m-p/1876367#M35898</guid>
      <dc:creator>Alfredo_Rubio</dc:creator>
      <dc:date>2024-05-28T13:57:53Z</dc:date>
    </item>
    <item>
      <title>Re: Emios interrupt on a Center Aligned Output PWM with Dead Time Insertion Buffered channel</title>
      <link>https://community.nxp.com/t5/S32K/Emios-interrupt-on-a-Center-Aligned-Output-PWM-with-Dead-Time/m-p/1877238#M35958</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;eMIOS channel interrupt is enabled in channel Control register's FEN bit. If set (and DMA bit is cleared) interrupt request to core is triggered when Sn[FLAG] is set.&amp;nbsp;&lt;BR /&gt;In OPWMCB mode flag is set either on training edge or both edges, based on MODE field setting.&lt;/P&gt;
&lt;P&gt;BR, Petr&lt;/P&gt;</description>
      <pubDate>Wed, 29 May 2024 11:23:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/Emios-interrupt-on-a-Center-Aligned-Output-PWM-with-Dead-Time/m-p/1877238#M35958</guid>
      <dc:creator>PetrS</dc:creator>
      <dc:date>2024-05-29T11:23:58Z</dc:date>
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