https://community.nxp.com/t5/S32K/Why-PIT-is-needed-in-S32K/m-p/1876551#M35910 <P>Hi&nbsp;<a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/231277">@deepika_16</a>,</P> <P><SPAN>PIT decrements from set value to zero and STM increments from zero to set value.</SPAN></P> <P>Also, all the PIT instances are capable of generating periodic triggers. PIT triggers are routed to motor control IPs such as eMIOS, LCU, BCTU, ADC etc. via TRGMUX.&nbsp;It also&nbsp;<SPAN>contains RTI which can be used for waking up from STOP mode and PIT can be used to trigger DMA.</SPAN></P> <P><SPAN>Best regards,<BR />Julián</SPAN></P> Tue, 28 May 2024 21:25:54 GMT Julián_AragónM 2024-05-28T21:25:54Z https://community.nxp.com/t5/S32K/Why-PIT-is-needed-in-S32K/m-p/1875929#M35856 <P>Why PIT is needed for partition of clock gating even though we are having STM timers based on core clock frequency we are supplying the clock to STM?</P> Tue, 28 May 2024 05:15:25 GMT https://community.nxp.com/t5/S32K/Why-PIT-is-needed-in-S32K/m-p/1875929#M35856 deepika_16 2024-05-28T05:15:25Z https://community.nxp.com/t5/S32K/Why-PIT-is-needed-in-S32K/m-p/1876551#M35910 <P>Hi&nbsp;<a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/231277">@deepika_16</a>,</P> <P><SPAN>PIT decrements from set value to zero and STM increments from zero to set value.</SPAN></P> <P>Also, all the PIT instances are capable of generating periodic triggers. PIT triggers are routed to motor control IPs such as eMIOS, LCU, BCTU, ADC etc. via TRGMUX.&nbsp;It also&nbsp;<SPAN>contains RTI which can be used for waking up from STOP mode and PIT can be used to trigger DMA.</SPAN></P> <P><SPAN>Best regards,<BR />Julián</SPAN></P> Tue, 28 May 2024 21:25:54 GMT https://community.nxp.com/t5/S32K/Why-PIT-is-needed-in-S32K/m-p/1876551#M35910 Julián_AragónM 2024-05-28T21:25:54Z