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    <title>topic Re: ECC FlexCAN Fault Injection Sequence &amp;amp; RTD Examples in S32K</title>
    <link>https://community.nxp.com/t5/S32K/ECC-FlexCAN-Fault-Injection-Sequence-amp-RTD-Examples/m-p/1869656#M35614</link>
    <description>&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/52961"&gt;@PetrS&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I tried to initialize memory as you suggested in previous post:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;You said:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;"yes, seems RTD is not fully correct with respect of ECC usage. This is disabled by default, i think, so does not bring any issue.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;So before you want to enable ECC you need to manually initialize RAM from offsets&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;0x80-0xAD and 0xC20-0x31FF (or just parts does not covered by FlexCAN_ClearRAM).:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I have a lot of problems to initialize it outside RTD, because, first you must enter in Freeze mode (and not sure if it is necessary to reset MCR[MDIS] or other stuff ), then clear CAN memory and finally (I think, disable freeze mode (and, maybe disable can....and probabilly some other stuff...)).&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;But happens to me that&amp;nbsp; sometimes MCU fails to enter in freeze mode and I don't know why .... and other&amp;nbsp; unpredictable behaviours.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Anyway in RM rev8&amp;nbsp; is reported as Follow (see point 3.):&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ECC_SEQUENCE.png" style="width: 814px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/279833i2C346CA5A0D5BE7E/image-size/large?v=v2&amp;amp;px=999" role="button" title="ECC_SEQUENCE.png" alt="ECC_SEQUENCE.png" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;So ALL flexcan memory is to be initialized only at step 3, after steps 1 and 2 !&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;FlexCAN_Init() follows exactly these steps and calls correctly&amp;nbsp;&amp;nbsp;FlexCAN_ClearRAM() function. The problem (or bug?) is&amp;nbsp; that function&amp;nbsp; doesen't initialize all&amp;nbsp;&amp;nbsp;&amp;nbsp;0x80-0xAD and&amp;nbsp;&amp;nbsp;0xC20-0x31FF (related to CAN_0) memory........... as requested by&amp;nbsp; R. manual.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;this is a big problem because:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;1) Fault Injection is not possible&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;2) also ECC runtime management, enabled by&amp;nbsp;FlexCAN_Ip_SetMemErrorDetection() could have some problems, because ECC parity bit are not cleared at init.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;So manual says that clear ram need to be performed at a specific initialization step (step 3), but RTD does't clear all memory. (ECC and Fault Inj are required by ASILD)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;What is the solution ?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Best regards,&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Tue, 21 May 2024 10:55:39 GMT</pubDate>
    <dc:creator>FabioG</dc:creator>
    <dc:date>2024-05-21T10:55:39Z</dc:date>
    <item>
      <title>ECC FlexCAN Fault Injection Sequence &amp; RTD Examples</title>
      <link>https://community.nxp.com/t5/S32K/ECC-FlexCAN-Fault-Injection-Sequence-amp-RTD-Examples/m-p/1863605#M35229</link>
      <description>&lt;P&gt;Hi There,&lt;/P&gt;&lt;P&gt;I am a little confused about the FlexCAN ECC fault-injection RTD driver sequence in particular:&lt;/P&gt;&lt;P&gt;1) Can you give me some examples ? I don't find anything in S32 studio nor in RTD examples nor in NXP community...&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;2) Anywhere another question is related to Reference manual rev8 page 2976&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ecc2.png" style="width: 845px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/278270i8CDA78AA46A51F97/image-size/large?v=v2&amp;amp;px=999" role="button" title="ecc2.png" alt="ecc2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;a) the initialization of all flexcan&amp;nbsp; memory address range and register (red-1) is done by FlexCAN_ip_Init() or must be done by user ?... I don't find any initialization in RTD and (red-2) I don't understand it, this bit should be set or reset, and what is the meaning of the statement?&lt;/P&gt;&lt;P&gt;3) is it necessary to call&amp;nbsp;FlexCAN_Init() before fault injection process ?. It seems it is not necessary (and this would be a good thing for my software structure)&lt;/P&gt;&lt;P&gt;4) I suppose that a correct sequence starts with :&lt;/P&gt;&lt;P&gt;FlexCAN_Ip_SetMemErrorDetection(INST_FLEXCAN_0,true);&lt;/P&gt;&lt;P&gt;FlexCAN_Ip_SetMemErrorDetectionInt(INST_FLEXCAN_0, FLEXCAN_ALL_ECC_ERROR, true);&lt;/P&gt;&lt;P&gt;FlexCAN_Ip_SetMemErrorInjection();&lt;/P&gt;&lt;P&gt;... ??...&lt;/P&gt;&lt;P&gt;Can you give me some help ?&lt;/P&gt;&lt;P&gt;Best Regards&lt;/P&gt;&lt;P&gt;Fabio&lt;/P&gt;</description>
      <pubDate>Fri, 10 May 2024 16:15:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/ECC-FlexCAN-Fault-Injection-Sequence-amp-RTD-Examples/m-p/1863605#M35229</guid>
      <dc:creator>FabioG</dc:creator>
      <dc:date>2024-05-10T16:15:16Z</dc:date>
    </item>
    <item>
      <title>Re: ECC FlexCAN Fault Injection Sequence &amp; RTD Examples</title>
      <link>https://community.nxp.com/t5/S32K/ECC-FlexCAN-Fault-Injection-Sequence-amp-RTD-Examples/m-p/1866264#M35409</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;1) unfortunately I am not aware of such example to test FlexCAN ECC&lt;BR /&gt;2) FlexCAN_Ip_Init is doing memory init calling&amp;nbsp;FlexCAN_ClearRAM, but it does not seem it clears all location stated in the RM, as far as I got the code&lt;BR /&gt;3) before ECC is tested a RAM must be initialized and it would be done by&amp;nbsp;FlexCAN_Ip_Init as documentation indicates.&lt;SPAN&gt;&amp;nbsp;FlexCAN_Init is called within&amp;nbsp;FlexCAN_Ip_Init so no need to call it again&lt;BR /&gt;4) that sequence seems to be right.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;BR, Petr&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 15 May 2024 11:48:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/ECC-FlexCAN-Fault-Injection-Sequence-amp-RTD-Examples/m-p/1866264#M35409</guid>
      <dc:creator>PetrS</dc:creator>
      <dc:date>2024-05-15T11:48:32Z</dc:date>
    </item>
    <item>
      <title>Re: ECC FlexCAN Fault Injection Sequence &amp; RTD Examples</title>
      <link>https://community.nxp.com/t5/S32K/ECC-FlexCAN-Fault-Injection-Sequence-amp-RTD-Examples/m-p/1866986#M35452</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Thank you &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/52961"&gt;@PetrS&lt;/a&gt;&amp;nbsp; for the answer,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;1)regarded point 2) of previous post, I checked too that FlexCAN_ClearRAM, called by FlexCAN_Init() clears a fewer part of the ram indicated in table "FlexCAN Error injection Map" par 73.1.2. p 2975 of RM rev8.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;What does it mean that this, do I have to initialize all&amp;nbsp; uninitialized register manually by myself for fault injection?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;2) In the project, I previous configured ECC error detection and correction for safety&amp;nbsp; punctual faults management, by calling&amp;nbsp;FlexCAN_Ip_SetMemErrorDetection(..,true) function and and configuring ECC in Normal Mode. But again, I checked that:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="INJECTION.png" style="width: 886px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/279081i243FA3C75AC5AE07/image-size/large?v=v2&amp;amp;px=999" role="button" title="INJECTION.png" alt="INJECTION.png" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;So also in runtime detection/correction mechanism, memory(CAN_BASE_ADDR related) from 0x80-0xAD and 0xC20-0x31FF must be initializated.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;But FlexCAN_Init() initialize a few part&amp;nbsp; of it.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;So does aspect me that runtime Safety Mechanism&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;does not function properly (also without latent faults mechanism (falultInj) developed)?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;3) Maybe there are other RTD functions that initializes missing ones ?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Best Regards&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Fabio&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 16 May 2024 08:54:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/ECC-FlexCAN-Fault-Injection-Sequence-amp-RTD-Examples/m-p/1866986#M35452</guid>
      <dc:creator>FabioG</dc:creator>
      <dc:date>2024-05-16T08:54:32Z</dc:date>
    </item>
    <item>
      <title>Re: ECC FlexCAN Fault Injection Sequence &amp; RTD Examples</title>
      <link>https://community.nxp.com/t5/S32K/ECC-FlexCAN-Fault-Injection-Sequence-amp-RTD-Examples/m-p/1867163#M35470</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;yes, seems RTD is not fully correct with respect of ECC usage. This is disabled by default, i think, so does not bring any issue.&lt;BR /&gt;So before you want to enable ECC you need to manually initialize RAM from offsets&amp;nbsp;&lt;SPAN&gt;0x80-0xAD and 0xC20-0x31FF (or just parts does not covered by FlexCAN_ClearRAM).&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;BR, Petr&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 16 May 2024 12:19:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/ECC-FlexCAN-Fault-Injection-Sequence-amp-RTD-Examples/m-p/1867163#M35470</guid>
      <dc:creator>PetrS</dc:creator>
      <dc:date>2024-05-16T12:19:15Z</dc:date>
    </item>
    <item>
      <title>Re: ECC FlexCAN Fault Injection Sequence &amp; RTD Examples</title>
      <link>https://community.nxp.com/t5/S32K/ECC-FlexCAN-Fault-Injection-Sequence-amp-RTD-Examples/m-p/1869656#M35614</link>
      <description>&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/52961"&gt;@PetrS&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I tried to initialize memory as you suggested in previous post:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;You said:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;"yes, seems RTD is not fully correct with respect of ECC usage. This is disabled by default, i think, so does not bring any issue.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;So before you want to enable ECC you need to manually initialize RAM from offsets&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;0x80-0xAD and 0xC20-0x31FF (or just parts does not covered by FlexCAN_ClearRAM).:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I have a lot of problems to initialize it outside RTD, because, first you must enter in Freeze mode (and not sure if it is necessary to reset MCR[MDIS] or other stuff ), then clear CAN memory and finally (I think, disable freeze mode (and, maybe disable can....and probabilly some other stuff...)).&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;But happens to me that&amp;nbsp; sometimes MCU fails to enter in freeze mode and I don't know why .... and other&amp;nbsp; unpredictable behaviours.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Anyway in RM rev8&amp;nbsp; is reported as Follow (see point 3.):&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ECC_SEQUENCE.png" style="width: 814px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/279833i2C346CA5A0D5BE7E/image-size/large?v=v2&amp;amp;px=999" role="button" title="ECC_SEQUENCE.png" alt="ECC_SEQUENCE.png" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;So ALL flexcan memory is to be initialized only at step 3, after steps 1 and 2 !&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;FlexCAN_Init() follows exactly these steps and calls correctly&amp;nbsp;&amp;nbsp;FlexCAN_ClearRAM() function. The problem (or bug?) is&amp;nbsp; that function&amp;nbsp; doesen't initialize all&amp;nbsp;&amp;nbsp;&amp;nbsp;0x80-0xAD and&amp;nbsp;&amp;nbsp;0xC20-0x31FF (related to CAN_0) memory........... as requested by&amp;nbsp; R. manual.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;this is a big problem because:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;1) Fault Injection is not possible&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;2) also ECC runtime management, enabled by&amp;nbsp;FlexCAN_Ip_SetMemErrorDetection() could have some problems, because ECC parity bit are not cleared at init.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;So manual says that clear ram need to be performed at a specific initialization step (step 3), but RTD does't clear all memory. (ECC and Fault Inj are required by ASILD)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;What is the solution ?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Best regards,&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 21 May 2024 10:55:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/ECC-FlexCAN-Fault-Injection-Sequence-amp-RTD-Examples/m-p/1869656#M35614</guid>
      <dc:creator>FabioG</dc:creator>
      <dc:date>2024-05-21T10:55:39Z</dc:date>
    </item>
    <item>
      <title>Re: ECC FlexCAN Fault Injection Sequence &amp; RTD Examples</title>
      <link>https://community.nxp.com/t5/S32K/ECC-FlexCAN-Fault-Injection-Sequence-amp-RTD-Examples/m-p/1880585#M36194</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;not sure what to comment more. If ECC is enabled then all memory area specified must be written in Freeze mode to properly set ECC parity bits, otherwise after leaving Freeze module could not work properly depending on error detected.&lt;BR /&gt;However if you manually init all needed area, it would work then.&amp;nbsp;FlexCAN_EnterFreezeMode_Privileged/FlexCAN_ExitFreezeMode_Privileged can be used to enter/leave Freeze mode.&lt;/P&gt;&lt;P&gt;BR, Petr&lt;/P&gt;</description>
      <pubDate>Tue, 04 Jun 2024 11:13:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/ECC-FlexCAN-Fault-Injection-Sequence-amp-RTD-Examples/m-p/1880585#M36194</guid>
      <dc:creator>PetrS</dc:creator>
      <dc:date>2024-06-04T11:13:23Z</dc:date>
    </item>
    <item>
      <title>Re: ECC FlexCAN Fault Injection Sequence &amp; RTD Examples</title>
      <link>https://community.nxp.com/t5/S32K/ECC-FlexCAN-Fault-Injection-Sequence-amp-RTD-Examples/m-p/1880729#M36204</link>
      <description>Thank you very much.&lt;BR /&gt;one very last question:&lt;BR /&gt;do you know if there is a change to the RTD driver in future releases to clear all ECC ram?</description>
      <pubDate>Tue, 04 Jun 2024 14:48:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/ECC-FlexCAN-Fault-Injection-Sequence-amp-RTD-Examples/m-p/1880729#M36204</guid>
      <dc:creator>FabioG</dc:creator>
      <dc:date>2024-06-04T14:48:12Z</dc:date>
    </item>
    <item>
      <title>Re: ECC FlexCAN Fault Injection Sequence &amp; RTD Examples</title>
      <link>https://community.nxp.com/t5/S32K/ECC-FlexCAN-Fault-Injection-Sequence-amp-RTD-Examples/m-p/1880914#M36214</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;let me ask SW team.&lt;/P&gt;
&lt;P&gt;BR, Petr&lt;/P&gt;</description>
      <pubDate>Tue, 04 Jun 2024 20:27:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32K/ECC-FlexCAN-Fault-Injection-Sequence-amp-RTD-Examples/m-p/1880914#M36214</guid>
      <dc:creator>PetrS</dc:creator>
      <dc:date>2024-06-04T20:27:27Z</dc:date>
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