https://community.nxp.com/t5/S32K/DMA-based-UART-using-LINFlexd/m-p/1836667#M33542 <P>Wrong community, please close this ticket. Identical ticket has been posted in the correct community for tracking.&nbsp;<a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/220394">@noorhasan</a>&nbsp;</P> <P>Thanks,</P> <P>Haoyue</P> Wed, 27 Mar 2024 18:49:50 GMT haoyue-yan 2024-03-27T18:49:50Z https://community.nxp.com/t5/S32K/DMA-based-UART-using-LINFlexd/m-p/1836404#M33525 <P>Hello,</P><P>&nbsp;</P><P>We are trying to use LINFlexd for UART communication in DMA based implementation.</P><P>While the same Linflexd channel can be used successfully when we use it with interrupt based implementation, I can't see data being transferred after the DMA0_Ch0 ISR is triggered for DMA based implementation.</P><P>Some of the inconsistencies that we observed is related to LIN register values when Tx is triggered.</P><P>When we select UART mode in UARTCR, as per the reference manual LINTCSR[mode] should always be set to 1 (UART mode). But, as shown in the screenshot below, it is still set in LIN mode, while UARTCR is in UART Mode.</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="noorhasan_0-1711547451176.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/270708i223CF004B6F26883/image-size/medium?v=v2&amp;px=400" role="button" title="noorhasan_0-1711547451176.png" alt="noorhasan_0-1711547451176.png" /></span></P><P>&nbsp;</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="noorhasan_1-1711547609551.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/270709iC174E43D03A9DDC6/image-size/medium?v=v2&amp;px=400" role="button" title="noorhasan_1-1711547609551.png" alt="noorhasan_1-1711547609551.png" /></span></P><P>&nbsp;</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="noorhasan_2-1711547619956.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/270710i63363E77C1D04FE0/image-size/medium?v=v2&amp;px=400" role="button" title="noorhasan_2-1711547619956.png" alt="noorhasan_2-1711547619956.png" /></span></P><P>&nbsp;</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="noorhasan_3-1711547666725.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/270711i2BD92C81B6AA9133/image-size/medium?v=v2&amp;px=400" role="button" title="noorhasan_3-1711547666725.png" alt="noorhasan_3-1711547666725.png" /></span></P><P>&nbsp;</P><P>&nbsp;</P><P>Further, the data registers are both showing not-accessible (????)</P><P>&nbsp;</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="noorhasan_4-1711547728682.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/270712iADC1D36909836C5F/image-size/medium?v=v2&amp;px=400" role="button" title="noorhasan_4-1711547728682.png" alt="noorhasan_4-1711547728682.png" /></span></P><P>&nbsp;</P><P>&nbsp;</P><P>Please help with this.</P><P>Thank you</P><P><a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/59182">@justinlydick</a>&nbsp;</P><P><a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/206644">@haoyue-yan</a>&nbsp;</P> Wed, 27 Mar 2024 13:58:01 GMT https://community.nxp.com/t5/S32K/DMA-based-UART-using-LINFlexd/m-p/1836404#M33525 noorhasan 2024-03-27T13:58:01Z https://community.nxp.com/t5/S32K/DMA-based-UART-using-LINFlexd/m-p/1836667#M33542 <P>Wrong community, please close this ticket. Identical ticket has been posted in the correct community for tracking.&nbsp;<a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/220394">@noorhasan</a>&nbsp;</P> <P>Thanks,</P> <P>Haoyue</P> Wed, 27 Mar 2024 18:49:50 GMT https://community.nxp.com/t5/S32K/DMA-based-UART-using-LINFlexd/m-p/1836667#M33542 haoyue-yan 2024-03-27T18:49:50Z